L9310 Datasheet, PDF (37/60 Pages) Agere Systems – Line Interface and Line Access Circuit Full-Feature SLIC,Ringing Relay,and Test Access Device

Data Sheet
July 2001
L9310 Line Interface and Line Access Circuit
Full-Feature SLIC, Ringing Relay, and Test Access Device
Applications (continued)
dc Characteristics (continued)
Battery Feed (continued)
50
1
10 kΩ
40
30
1
Rdc
20
10
0
0 5 10 15 20 25 30 35 40 45
LOOP VOLTAGE (V)
Notes:
VBAT1 = –48 V.
VBAT2 = –24 V.
ILIM = 40 mA (RPROG = 66.5 kΩ).
12-3050.g (F)
Figure 14. L9310 Loop Current vs. Loop Voltage
Starting from the on-hook condition and going through
to a short circuit, the curve passes through two regions:
Region 1: On-hook and low loop currents: the slope
corresponds to the dc feed resistance of the SLIC (plus
any series resistance). The open-circuit voltage is the
battery voltage less the overhead voltage of the device.
Region 2: Current limit: the dc current is limited to a
value determined by VPROG. This region of the dc tem-
plate has a high resistance (10 kΩ).
Notice that the I-V curve is uninterrupted when the
power is shifted from the high-voltage battery to the
low-voltage battery (if auxiliary battery option is used).
This is shown in Figure 12 in the Automatic Battery
Switch section.
Battery Reversal Rate
The rate of battery reverse is controlled or ramped by
capacitors FB1 and FB2. A chart showing FB1 and FB2
values versus typical ramp time is given below. Leave
FB1 and FB2 open if it is not desired to ramp the rate of
battery reversal.
Agere Systems Inc.
Table 19. FB1 and FB2 Values vs. Typical
Ramp Time
CFB1 and CFB2*
0.01 µF
0.1 µF
0.22 µF
0.47 µF
1.0 µF
1.22 µF
1.3 µF
1.4 µF
1.6 µF
Transition Time
20 ms
220 ms
440 ms
900 ms
1.8 s
2.25 s
2.5 s
2.7 s
3.2 s
* Typical recommended value for CFB1 and CFB2 is less
than 0.033 µF.
Longitudinal to Metallic Balance
Longitudinal to metallic balance at PT/PR is specified in
the Electrical Characteristics section of this data sheet.
Supervision
Loop Closure
Loop closure supervision threshold is programmed via
an applied voltage source or ground, through a resistor
at the LCTH input. Loop closure status is presented at
the NSTAT output. NSTAT is an unlatched output that
represents either the loop closure or ring trip status,
depending on the device state. See Table 2 and
Table 3 for more details. Loop closure threshold current
(ILCTH) is set by:
2----5---0----(_--V-----R_---E_---F_----–_-----V----L_---C_---T_---H_----)
RLCTH (kΩ)
= ILCTH (mA)
where:
RLCTH is a resistor from the LCTH node to ground or a
voltage source.
VLCTH is ground or an external voltage source.
There is a built-in hysteresis associated with the loop
closure detector. The above equation describes the on-
hook to off-hook threshold. To help prevent false
glitches, the off-hook to on-hook threshold will be a typ-
ical 20% lower than the corresponding on-hook to off-
hook threshold.PPM injection can cause false loop clo-
sure indication. Connect a 0.01 µF capacitor to a 0.1 µF
capacitor from this node, LCF to VCC to filter the loop
closure detector the larger the capacitor the higher the
filtering. If loop closure filtering is not required, leave
LCF open.
37