ORT82G5 Datasheet, PDF (36/92 Pages) Agere Systems – ORCA ORT82G5 1.0.1-25/2.0-2.5/3.125 Gbits/s Backplane Interface FPSC

ORCA ORT82G5 FPSC Eight-Channel
1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet
July 2001
Memory Map
Definition of Register Types
The registers in ORT82G5 are 8-bit memory locations, which in general can be classified into the following types:
Status Register and Control Register.
Status Register
Read-only register to convey the status information of various operations within the FPSC core. An example is the
state of the XAUI link-state-machine.
Control Register
Read-write register to set up the control inputs that define the operation of the FPSC core.
The SERDES block within the ORT82G5 core has a set of status and control registers for it’s operation. The
detailed description of them can be found in the SERDES data sheet.
There is another group of status and control registers which are implemented outside the SERDES, which are
related to the SERDES and other functional blocks in the FPSC core. They will be described in detail here. Each
SERDES has four independent channels, which are named A, B, C, or D. Using this nomenclature, the SERDES A
channels are named as AA, AB, AC, and AD, while SERDES B channels will be BA, BB, BC, and BD.
Table 11. Structural Register Elements
Address (Hex)
Description
300xx
SERDES A, internal registers.
301xx
SERDES B, internal registers.
308xx
Channel A [A:D] registers (external to SERDES blocks).
309xx
Channel B [A:D] registers (external to SERDES blocks).
30A0x
Global registers (external to SERDES blocks).
A full memory map is included in Table 12.
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