OR3T20 Datasheet, PDF (154/210 Pages) Agere Systems – 3C and 3T Field-Programmable Gate Arrays

ORCA Series 3C and 3T FPGAs
Data Sheet
June 1999
Pin Information (continued)
Compatibility with OR2C/TxxA Series
The pinouts shown for the OR3Cxx and OR3Txxx devices are consistent with the OR2C/TxxA Series for all devices
offered in the same packages. This includes the following pins: VDD, VSS, VDD5 (OR2TxxA Series only), and all
configuration pins.
The following restrictions apply:
1. There are two configuration modes supported in the OR2C/TxxA Series that are not supported in Series 3: mas-
ter parallel down and synchronous peripheral modes. The Series 3 FPGAs have two new microprocessor inter-
face (MPI) configuration modes that are unavailable in the OR2C/TxxA Series.
2. There are four pins—one per each device side—that are user I/O in the OR2C/TxxA Series which can only be
used as fast dedicated clocks or global inputs in Series 3. These pins are also used to drive the ExpressCLK to
the I/O FFs on their given side of the device. These four middle ExpressCLK pins should not be used to connect
to a programmable clock manager (PCM). A corner ExpressCLK input should be used instead (see item 3
below). See Table 69 for a list of these pins in each package.
3. There are two other pins that are user I/O in both the OR2C/TxxA and Series 3 but also have optional added
functionality. Each of these pins drives the ExpressCLKs on two sides of the device. They also have fast connec-
tivity to the programmable clock manager (PCM). See Table 69 for a list of these pins in each package.
Table 69. Series 3 ExpressCLK Pins
Pin Name/
Package
I-ECKL
I-ECKB
I-ECKR
I-ECKT
I/O-SECKLL
I/O-SECKUR
208-Pin
240-Pin
SQFP/SQFP2 SQFP/SQFP2
22
26
80
91
131
152
178
207
49
56
159
184
256-Pin
PBGA
K3
W11
K18
B11
W1
A19
352-Pin
PBGA
N2
AE14
N23
B14
AB4
A25
432-Pin
EBGA
R29
AH16
T2
C15
AG29
D5
600-Pin
EBGA
U33
AM18
V2
C17
AK34
D5
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