TTSV02622 Datasheet, PDF (1/64 Pages) Agere Systems – STS-24 Backplane Transceiver

Data Sheet
June 2003
TTSV02622 STS-24 Backplane Transceiver
Features
s Allows wide range of applications for SONET net-
work termination application as well as generic
data moving for high-speed backplane data
transfer.
s Clock/data recovery (CDR) function for high-speed
serial backplane data transfer.
s CDR function uses Agere Systems Inc. proven
622 Mbits/s serial interface core.
s Two-channel CDR function provides 622 Mbits/s
serial interface per channel for a total chip
bandwidth of 1.24 Gbits/s (full duplex).
s Low-voltage differential signaling (LVDS) I/Os for
CDR and reference clock signals.
s 8:1 data multiplexing/demultiplexing (MUX/
deMUX) for 77.76 MHz byte-wide data processing.
s CDR meets B jitter tolerance specification of ITU-T
recommendation G.958.
s Powerdown option of CDR receiver on a per-
channel basis.
s Pseudo-SONET protocol including A1/A2 framing.
s SONET scrambling and descrambling for required
ones density (optional).
s Selected transport overhead (TOH) bytes insertion
and detection for interdevice communication via
the TOH serial link.
s Streamlined pointer processor (pointer mover) for
8 kHz frame alignment.
s FIFOs for alignment of incoming data to reference
clock.
s FIFOs optionally align incoming data across all two
channels for synchronous transport signal STS-24
operation (in dual STS-12 format).
s Independent data stream enables in pseudo-
SONET processor.
s Supports STS-12/STS-24 redundancy by either
software or hardware control for protection
switching applications.
s Low-power 3.3 V supply.
s –40 °C to +125 °C industrial temperature range.
s 272-pin ball grid array (PBGA) package.
Description
The TTSV02622 can support a 1.24 Gbits/s interface
for backplane connections. The 1.24 Gbits/s inter-
face is implemented as dual 622 Mbits/s LVDS links.
The HSI macrocell is used for clock/data recovery
(CDR) and MUX/deMUX between 77.76 MHz byte-
wide internal data buses and the 622 Mbits/s external
serial links.
Each 622 Mbits/s serial link uses a pseudo-SONET
protocol. SONET A1/A2 framing is used on the link
for locating the 8 kHz frame location. The link is also
scrambled using the standard SONET scrambler def-
inition to ensure proper transitions on the link for
improved CDR performance. Selectable transport
overhead (TOH) bytes are insertable in the transmit
direction. All bytes can be transparently passed
through the device, or all bytes can be inserted via
the TOH serial link. In addition, certain microproces-
sor unit (MPU) selectable bytes can be passed
through transparently while in insert mode.
Elastic buffers (FIFOs) are used to align each incom-
ing STS-12 link to the core 77.76 MHz clock and
8 kHz frame. These FIFOs will absorb delay varia-
tions between 622 Mbits/s links due to timing skews
between cards and along backplane traces. For
greater variations, a streamlined pointer processor
(pointer mover) within the device will align the 8 kHz
frames regardless of their incoming frame position.
The TTSV02622 supports dual STS-12 mode of
operation on the input/output ports. STS-24 is also
supported, but it must be received in the dual
STS-12 format. When operating in dual STS-12
mode, each of the independent byte streams carries
an entire STS-12 within it. Figure 1 on page 2 reveals
the byte ordering of the individual STS-12 streams.