TTRN012G5 Datasheet, PDF (1/22 Pages) Agere Systems – TTRN012G5 (2.5 Gbits/s) and TTRN012G7 (2.5 Gbits/s and 2.7 Gbits/s) Clock Synthesizer, 16:1 Data Multiplexer

Preliminary Data Sheet
August 2000
TTRN012G5 (2.5 Gbits/s) and TTRN012G7 (2.5 Gbits/s and 2.7 Gbits/s)
Clock Synthesizer, 16:1 Data Multiplexer
Features
s TTRN012G5 supports OC-48/STM-16 data rate
s TTRN012G7 supports:
— OC-48/STM-16 data rate
— RS (255, 239) forward error correction (FEC)
OC-48/STM-16 data rate
s Fully integrated clock synthesizer and 16:1 data
multiplexer
s Supports clockless data transfer into the 16:1
multiplexer
s Parity checking and valid data indication
s Data inversion option
s Additional high-speed CML serial data output for
system loopback
s Loss of lock indication
s Single 3.3 V supply
s Available in either MBIC 025 BiCMOS technology
or lower-power MBIC 025 silicon germanium
BiCMOS technology
s LVPECL 155.52 Mbits/s digital I/O
s Jitter generation and jitter transfer compliant with
the following:
— Telcordia Technologies* GR-253
— ITU-T G.825
— ITU-T G.958
Applications
s SONET/SDH line origination equipment
s SONET/SDH add/drop multiplexers
s SONET/SDH cross connects
s SONET/SDH test equipment
s Digital video transmission
* Telcordia Technologies is a registered trademark of Bell Com-
munications Research, Inc.
Description
The Lucent Technologies Microelectronics Group
TTRN012G5 operates at the OC-48/STM-16 data
rate of 2.5 Gbits/s. The TTRN012G7 device operates
at either 2.5 Gbits/s or the RS FEC OC-48/STM-16
data rate of 2.7 Gbits/s. For clarity, this data sheet
refers to the TTRN012G5 serial data rate as
2.5 Gbits/s and the parallel data and reference clock
frequency as 155 MHz. (The precise rates are
2.48832 Gbits/s and 155.52 MHz.) When using the
TTRN012G7 at the FEC rate, the 2.5 Gbits/s data
rate should be interpreted as 2.7 Gbits/s and the par-
allel and clock frequency should be interpreted as
166 MHz. (The precise rates are 2.66606 Gbits/s and
166.62 MHz.)
The devices provide a 16:1 multiplexer and clock
multiplier unit. Both a high-speed serial clock and
data output are generated. The devices accept 16
differential PECL data inputs and a low-speed refer-
ence clock. A unique feature of the multiplexer is that
no clock is required to feed in the 16 data lines, as
long as the upstream data chip clock is synchronous
with the device REFCLKP/N input.
Alternatively, contra-clocking may be used, whereby
the device provides one of four phases of a
155.52 MHz or 166.62 MHz clock output back
upstream to the data chip.
Other features include a parity bit input and parity
check on the 16 input data lines, a second
2.5 Gbits/s or 2.7 Gbits/s data output for loopback
toward the TRCV012G5 or TRCV012G7 device, and
a user-configurable PLL bandwidth. Both devices are
available in either BiCMOS or in SiGe BiCMOS tech-
nology for lower power operation.