TMPR28051 Datasheet, PDF (1/90 Pages) Agere Systems – TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 5 of the Device

Advisory
August 5, 1999
TMPR28051 STS-1/AU-3 (STM-0) Mapper
Device Advisory for Version 5 of the Device
Register Architecture (RA) Map
RA-1. Reset Bit
The software reset bit (bit 0) of register 0x00 is not functional.
RA-2. Transmit Path AIS Insert Bit
The TXPAISINS bit (bit 5) of register 0x01 produces both AIS-P and AIS-L.
RA-3. STS-1 Loss of Pointer Mask Bit
The STS1LOPMSK bit (bit 2) of register 0x04 masks both STS1LOP and STS1LOF.
RA-4. STS-1 Loss of Frame Mask Bit
The STS1LOFMSK bit (bit 1) of register 0x04 is not functional.
RA-5. VTLABCOM and VTRFIRDICOM Interrupt Bits
Occasionally, it might require multiple reads to clear the composite interrupt bits VTLABCOM (bit 2 of
register 0x05) and VTRFIRDICOM (bit 4 of register 0x05).
Error Insertion (EI)
EI-1. DS1/E1 Alarm Indication Signal
The device does not insert DS1/E1 AIS towards the STS-1 if there is an LOC condition in the incoming DS1/E1
signal.
EI-2. LOC Condition in E1 Loopback Mode
In the absence of an input clock, the device detects an LOC condition and generates TU-AIS upstream, even if the
loopback path is selected (the loopback signal is overwritten by TU-AIS).