TAAD08JU2 Datasheet, PDF (1/174 Pages) Agere Systems – T1/E1/J1 ATM Processor, Versions 2.1 and 3.1

Preliminary Data Sheet
August 18, 2003
TAAD08JU2
T1/E1/J1 ATM Processor, Versions 2.1 and 3.1
1 Features
s System-on-a-chip integrated circuit supports low-
speed ATM access for next-generation wireless
base transmission station (BTS), base station con-
troller (BSC), node-B, radio network controller
(RNC), and remote access concentrator (RAC)
applications.
s IC provides an integrated octal framer that sup-
ports T1/E1/J1 formats.
s Supports inverse multiplexing for ATM (IMA) over
selected group and link mappings ranging from
four two-link groups up to one eight-link group per
ATM Forum AF-PHY-0086.001.
s Integrates an ATM adaptation layer 2 (AAL2) seg-
mentation and reassembly (SAR) function for sup-
port of low-speed data or voice traffic per ITU
I.363.2.
s Provides AAL5 SAR functionality per ITU I.363.5.
s Provides quality of service (QoS) connection iden-
tifier (CID) multiplexing per ITU I.366.1.
s Enables ATM layer user network interface (UNI) or
IMA mode, selectable on a per-link basis for flexi-
ble transport of delay critical voice and data traffic.
s Guarantees QoS for a variety of traffic types
(including delay-sensitive voice, real-time data,
non-real-time data, and signaling information)
through an advanced hierarchical three-level prior-
ity scheduler and per-VC queueing.
s Supports 2032 bidirectional AAL2 CIDs.
s Supports 2032 bidirectional high-speed data con-
nections or virtual circuits (VCs) via embedded
context memory; filters control cells and accepts
control cells via a host microprocessor interface.
s On-board memory is used for connection manage-
ment and queue data storage. No external memory
is needed.
s Software package includes the following:
— Device manager source code (C-based device
manager ready-to-use with host RTOS).
— Setup file utility to provision TAAD08JU2.
— Firmware for embedded controller (executable
binary).
— API reference manual available for device man-
ager software.
s Designed in 0.16 µm, low-power CMOS
technology.
2 Physical
s 3.3 V digital I/O compatibility; 1.5 V core power
s 520 enhanced ball-grid array (EBGA) package
s –40 ^oC to +85 ^oC temperature range
3 Standards
ITU I.363.2, ITU I.363.5, ITU I.366.1, ITU I.366.2,
ITU I.432, ITU I.361, ITU I.371, ITU G.703, ITU
G.704, ITU G.804, ITU G.732, ITU G.706, ITU I.610,
ITU G.775, ITU G.733, ITU G.735, ITU G.965,
ITU O.162, ANSI^® T1.403, ANSI T1.231,
ATM Forum AF-PHY-0086.001
ATM Forum AF-PHY-0039.000
ATM Forum AF-TM-0121.000
ETS 300.417-1-1