LCK4993 Datasheet, PDF (1/25 Pages) Agere Systems – Low-Voltage PLL Clock Drivers

Data Sheet, Revision 1
May 5, 2004
LCK4993/LCK4994
Low-Voltage PLL Clock Drivers
1 Features
s 12 MHz—100 MHz (LCK4993), or 24 MHz—200 MHz
(LCK4994) output operation
s Matched pair output skew <200 ps
s Zero input-to-output delay
s 18 LVTTL 50% duty-cycle outputs capable of driving
50 Ω terminated lines
s 3.3 V/2.5 V LVTTL/LV differential (LVPECL) fault tolerant
and hot insertable reference inputs
s Phase adjustments from 625 ps up to 1300 ps steps up
to ±10.4 ns
s Output divide ratios of (1—6, 8, 10, 12)
s Multiply ratios of (1—6, 8) x input frequency
s Individual output bank disable for aggressive power
management and EMI reduction
s Output high-impedance (HI-Z) option for testing
purposes
s Fully integrated PLL with lock indicator
s Single 3.3 V/2.5 V ± 10% supply
s 100-pin TQFP package
s 100-ball FSBGA package
s Pin-for-pin compatible with CYPRESS^® CY7B993V and
CY7B994V
2 Description
The LCK4993 and LCK4994 low-voltage PLL clock drivers
offer user-selectable control over system clock functions.
The multiple-output clock drivers provide the system
integrator with functions necessary to optimize the timing of
high-performance computer and communication systems.
Each of the eighteen configurable outputs drive terminated
transmission lines with impedances as low as 50 Ω while
delivering minimal and specified output skews at LVTTL
levels. The outputs are arranged in five banks. Banks 1—4
allow a divide function of 1 to 12, while simultaneously
allowing phase adjustments in 625 ps—1300 ps increments
up to 10.4 ns. One of the output banks also includes an
independent clock invert function. The feedback bank
consists of two outputs that allow divide-by functionality
from 1 to 12 and limited phase adjustments. Any one of
these eighteen outputs can be connected to the feedback
input or drive other inputs.
Selectable reference input is a fault tolerance feature that
allows smooth change over to the secondary clock source
when the primary clock source is not in operation. The
reference inputs and feedback inputs are configurable to
accommodate both LVTTL or differential (LVPECL) inputs.
The completely integrated PLL reduces jitter and simplifies
board layout.