LCK4310 Datasheet, PDF (1/10 Pages) Agere Systems – Low-Voltage PLL Clock Driver

Data Sheet
April 20, 2004
LCK4310
Low-Voltage PLL Clock Driver
1 Features
s Output operating frequencies up to 1.25 GHz max.
s 100 ps part–to–part skew.
s 40 ps typical output–to–output skew.
s Cycle-to-cycle jitter 5 ps max.
s 3.3 V and 2.5 V compatible.
s Internal input pulldown resistors.
s Q output will default low with inputs open or at VEE.
s Meets or exceeds Joint Electron Device Engineering
Council (JEDEC) specification EIA^®/JESD78 IC latchup
test.
s Moisture sensitivity level 1.
s Flammability rating: UL^®–94 code V–0 at 1/8 in., oxygen
index 28 to 34.
s Pin-for-pin compatible with ON Semiconductor^® part
number MC100LVE310.
2 Description
The LCK4310 is a low-voltage, low-skew 2:8 differential
emitter-coupled logic (ECL) fanout buffer designed with
clock distribution in mind. The device features fully
differential clock paths to minimize both device and system
skew. The LCK4310 offers two selectable clock inputs to
allow for redundant or test clocks to be incorporated into
the system clock trees.
To ensure that the tight skew specification is met, it is
necessary that both sides of the differential output are
terminated into 50 Ω, even if only one side is being used. In
most applications, all eight differential pairs will be used
and therefore terminated. In the case where fewer than
eight pairs are used and in order to maintain minimum
skew, it is necessary to terminate at least the output pairs
adjacent to the output pair being used. Failure to follow this
guideline will result in small degradations of propagation
delay (on the order of 10 ps—20 ps) of the outputs being
used. While not catastrophic to most designs, this will result
in an increase in skew.
Note: The package corners isolate outputs from one anoth-
er such that the guideline expressed above holds only
for outputs on the same side of the package.
The LCK4310, as with most ECL devices, can be operated
from a positive voltage supply (VDD) in LVPECL mode. This
allows the LCK4310 to be used for high-performance clock
distribution in 3.3 V/2.5 V systems. Designers can take
advantage of the LCK4310’s performance to distribute low-
skew clocks across the backplane or the board. In a PECL
environment (series or Thevenin), line terminations are
typically used since they require no additional power
supplies. If parallel termination is desired, a terminating
voltage of VDD – 2.0 V will need to be provided.
An internally generated voltage supply (VBB pin) is
available to this device only. For single-ended input
conditions, the unused differential input is connected to
VBB as a switching reference voltage. VBB may also rebias
ac coupled inputs. When used, decouple VBB and VDD via a
0.01 µF capacitor and limit current sourcing or sinking to
0.5 mA. When not used, VBB should be left open.