FW803 Datasheet, PDF (1/24 Pages) Agere Systems – PHY IEEE 1394A Three-Cable Transceiver/Arbiter Device

Data Sheet, Rev. 3
June 2001
FW803 PHY IEEE * 1394A
Three-Cable Transceiver/Arbiter Device
Distinguishing Features
I Compliant with IEEE P1394a Draft 2.0 Standard
for a High Performance Serial Bus (Supplement)
I Supports extended BIAS_HANDSHAKE time for
enhanced interoperability with camcorders.
I While unpowered and connected to the bus, will not
drive TPBIAS on a connected port even if receiving
incoming bias voltage on that port.
I Does not require external filter capacitors for PLL.
I Does not require a separate 5 V supply for 5 V link
controller interoperability.
I Interoperable across 1394 cable with 1394 physical
layers (PHY) using 5 V supplies.
I Interoperable with 1394 link-layer controllers using
5 V supplies.
I Powerdown features to conserve energy in battery-
powered applications include:
— Device powerdown pin.
— Link interface disable using LPS.
— Inactive ports power down.
I Interface to link-layer controller supports Annex J
electrical isolation as well as bus-keeper isolation.
Features
I Provides three fully compliant cable ports at
100 Mbits/s, 200 Mbits/s, and 400 Mbits/s.
I Fully supports open HCI requirements.
I Supports arbitrated short bus reset to improve
utilization of the bus.
I Supports ack-accelerated arbitration and fly-by con-
catenation.
I Supports connection debounce.
I Supports multispeed packet concatenation.
I Supports PHY pinging and remote PHY access
packets.
I Fully supports suspend/resume.
I Supports PHY-link interface initialization and reset.
I Supports 1394a-2000 register set.
I Supports LPS/link-on as a part of PHY-link interface.
I Supports provisions of IEEE 1394-1995 Standard for
a High Performance Serial Bus.
I Fully interoperable with FireWire^† implementation of
IEEE 1394-1995.
I Reports cable power fail interrupt when voltage at
CPS pin falls below 7.5 V.
I Separate cable bias and driver termination voltage
supply for each port.
Other Features
I 64-pin TQFP package.
I Single 3.3 V supply operation.
I Data interface to link-layer controller provided
through 2/4/8 parallel lines at 50 Mbits/s.
I 25 MHz crystal oscillator and PLL provide transmit/
receive data at 100 Mbits/s, 200 Mbits/s, and
400 Mbits/s, and link-layer controller clock at
50 MHz.
I Node power-class information signaling for system
power management.
I Multiple separate package signals provided for ana-
log and digital supplies and grounds.
Description
The Agere Systems Inc. FW803 device provides the
analog physical layer functions needed to implement a
three-port node in a cable-based IEEE 1394-1995 and
IEEE 1394a-2000 network.
* IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
† FireWire is a registered trademark of Apple Computer, Inc.