FW802C Datasheet, PDF (1/24 Pages) Agere Systems – FW 802C LOW - POWER IEEE 1394A-2000 TWO CABLE TRANSCEIVER/ ARBITER DEVICE

FW802C Low-Power PHY IEEE^® 1394A-2000
Two-Cable Transceiver/Arbiter Device
Data Sheet, Rev. 1
October 2002
™
Distinguishing Features
s Compliant with IEEE Standard 1394a-2000, IEEE
Standard for a High Performance Serial Bus
Amendment 1.
s Low-power consumption during powerdown or
microlow-power sleep mode.
s Supports extended BIAS_HANDSHAKE time for
enhanced interoperability with camcorders.
s While unpowered and connected to the bus, the
device will not drive TPBIAS on a connected port
even if receiving incoming bias voltage on that port.
s Does not require external filter capacitors for PLL.
s Does not require a separate 5 V supply for 5 V link
controller interoperability.
s Interoperable across 1394™ cable with 1394 physi-
cal layers (PHY) using 5 V supplies.
s Interoperable with 1394 link-layer controllers using
5 V supplies.
s 1394a-2000 compliant common-mode noise filter
on incoming TPBIAS.
s Powerdown features to conserve energy in battery-
powered applications include:
— Device powerdown pin.
— Link interface disable using LPS.
— Inactive ports powerdown.
— Automatic microlow-power sleep mode during
suspend.
s Interface to link-layer controller supports Annex J
electrical isolation as well as bus-keeper isolation.
Features
s Provides two compliant cable ports at 100 Mbits/s,
200 Mbits/s, and 400 Mbits/s.
s Supports OHCI requirements.
s Supports arbitrated short bus reset to improve
utilization of the bus.
s Supports ack-accelerated arbitration and fly-by con-
catenation.
s Supports connection debounce.
s Supports multispeed packet concatenation.
s Supports PHY pinging and remote PHY access
packets.
s Supports full suspend/resume.
s Supports PHY-link interface initialization and reset.
s Supports 1394a-2000 register set.
s Supports LPS/link-on as a part of PHY-link inter-
face.
s Supports provisions of IEEE 1394-1995 Standard
for a High Performance Serial Bus.
s Fully interoperable with FireWire^® implementation
of IEEE 1394-1995.
s Reports cable power fail interrupt when voltage at
CPS pin falls below 7.5 V.
s Separate cable bias and driver termination voltage
supply for each port.
s Meets Intel ^® Mobile Power Guideline 2000.
Other Features
s 48-pin TQFP package.
s Single 3.3 V supply operation.
s Data interface to link-layer controller provided
through 2/4/8 parallel lines at 50 Mbits/s.
s 25 MHz crystal oscillator and PLL provide transmit/
receive data at 100 Mbits/s, 200 Mbits/s, and
400 Mbits/s, and link-layer controller clock at
50 MHz.
s Node power-class information signaling for system
power management.
s Multiple separate package signals provided for ana-
log and digital supplies and grounds.