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FW32305 Datasheet, PDF (1/152 Pages) Agere Systems – 1394A PCI PHY/Link Open Host Controller Interface | |||
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Data Sheet, Rev. 2
October 2001
FW323 05
1394A PCI PHY/Link Open Host Controller Interface
Features
s 1394a-2000 OHCI link and PHY core function in sin-
gle device:
â Enables smaller, simpler, more efficient mother-
board and add-in card designs by replacing two
components with one
â Enables lower system costs
â Leverages proven 1394a-2000 PHY core design
â Demonstrated compatibility with current Microsoft
Windows ® drivers and common applications
â Demonstrated interoperability with existing, as well
as older, 1394 consumer electronics and periph-
erals products
â Feature-rich implementation for high performance
in common applications
â Supports low-power system designs (CMOS
implementation, power management features)
â Provides LPS, LKON, and CNA outputs to support
legacy power management implementations
s OHCI:
â Complies with OHCI 1.1 WHQL requirements
â Complies with Microsoft Windows Logo Program
System and Device Requirements
â Listed on Windows Hardware Compatibility List
http://www.microsoft.com/hcl/results.asp
â Compatible with Microsoft Windows and MacOS ®
operating systems
â 4 Kbyte isochronous transmit FIFO
â 2 Kbyte asynchronous transmit FIFO
â 4 Kbyte isochronous receive FIFO
â 2 Kbyte asychronous receive FIFO
â Dedicated asynchronous and isochronous
descriptor-based DMA engines
â Eight isochronous transmit contexts
â Eight isochronous receive contexts
â Prefetches isochronous transmit data
â Supports posted write transactions
s 1394a-2000 PHY core:
â Compliant with IEEE ® 1394a-2000, Standard for a
High Performance Serial Bus (Supplement)
â Provides three fully compliant cable ports, each
supporting 400 Mbits/s, 200 Mbits/s, and
100 Mbits/s traffic
â Supports extended BIAS_HANDSHAKE time for
enhanced interoperability with camcorders
â While unpowered and connected to the bus, will
not drive TPBIAS on a connected port even if
receiving incoming bias voltage on that port
â Does not require external filter capacitor for PLL
â Supports PHY core-link interface initialization and
reset
â Supports link-on as a part of the internal
PHY core-link interface
â 25 MHz crystal oscillator and internal PLL provide
transmit/receive data at 100 Mbits/s, 200 Mbits/s,
and 400 Mbits/s, and internal link-layer controller
clock at 50 MHz
â Interoperable across 1394 cable with 1394 phys-
ical layers (PHY core) using 5 V supplies
â Node power-class information signaling for
system power management
â Supports ack-accelerated arbitration and fly-by
concatenation
â Supports arbitrated short bus reset to improve
utilization of the bus
â Fully supports suspend/resume
â Supports connection debounce
â Supports multispeed packet concatenation
â Supports PHY pinging and remote PHY access
packets
â Reports cable power fail interrupt when voltage at
CPS pin falls below 7.5 V
â Separate cable bias and driver termination voltage
supply for each port
s Link:
â Cycle master and isochronous resource manager
capable
â Supports 1394a-2000 acceleration features
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