DNC3X3425 Datasheet, PDF (1/32 Pages) Agere Systems – DNC3X3425 Quad 10/100 Mbits/s Ethernet Transceiver Macrocell

Advance Data Sheet
March 2000
DNC3X3425
Quad 10/100 Mbits/s Ethernet Transceiver Macrocell
Features
Quad 100 Mbits/s FX Transceiver
Quad 10 Mbits/s Transceiver
s DSP based.
s Compatible with IEEE * 802.3 10Base-T standard
for twisted-pair cable.
s Half- and full-duplex operations.
s Autopolarity detection and correction.
s Adjustable squelch level for extended wire-length
capability (two levels).
s Compatible with IEEE 802.3u 100Base-FX stan-
4
dard.
s Reuses existing twisted-pair I/O pins for compatible
fiber-optic transceiver pseudo-ECL (PECL) data.
s Fiber mode automatically configures port:
— FX mode enable is pin or register selectable
— Disables autonegotiation and 10Base-T.
— Enables 100Base-FX remote fault signaling.
— Disables MLT-3 encoder/decoder.
— Disables scrambler/descrambler.
s Interfaces with IEEE 802.3u media independent
interface (MII) or a serial 10 Mbits/s 7-pin interface.
s On-chip filtering eliminates the need for external fil-
ters.
Quad 100 Mbits/s Transceiver
s Compatible with IEEE 802.3u MII (clause 22),
PCS/PMA (clause 24), PMD (clause 25), MII man-
agement, and autonegotiation (clause 28) specifi-
cations.
s Selectable 5-bit code-group (PDT/PDR interface)
or 4-bit data nibbles (MII interface) I/O.
s Full- or half-duplex operations.
s Optional carrier integrity monitor (CIM).
s Selectable carrier sense signal generation (MCRS)
asserted during either transmission or reception in
half duplex (MCRS asserted during reception only
in full duplex).
s Adaptive equalization and baseline wander correc-
tion.
s On-chip filtering eliminates the need for external
filters.
* IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
General
s Ports individually configurable
s Autonegotiation and management:
— Fast link pulse (FLP) burst generator.
— Arbitration function.
— Accepts preamble suppression.
— Operates up to 12.5 MHz.
s Supports the MII station management protocol and
frame format (clause 22): basic and extended reg-
ister set.
s Supports next page.
s Provides status signals: receive activity, transmit
activity, full duplex, collision/jabber, link integrity,
and speed indication.
s Powerdown mode for 10 Mbits/s and 100 Mbits/s
operation.
s Loopback testing for 10 Mbits/s and 100 Mbits/s
operation.
s 0.25 µm low-power CMOS technology.
s Single 3.3 V power supply operation.
s 25 MHz XTAL oscillator input or 25 MHz/50 MHz/
125 MHz clock input.
s Compatible with RMII (standard version) and SMII
(standard version).
Note: Advisories are issued as needed to update product information. When using this data sheet for design purposes, please contact
your Lucent Technologies Microelectronics Group Account Manager to obtain the latest advisory on this product.