AA88368AP Datasheet, PDF (7/15 Pages) Agamem Microelectronic Inc. – 10-BIT DAC

AA88368AP Agamem Mircoelectronics Inc.
PRELIMINARY
10-BIT DAC
„ FUNCTIONAL DESCRIPTION
DEVICE CONFIGURATION
As illustrated in Figure 3 Block Diagram, AA88368AP is composed by digital block and analog block.
The digital block consists of a Shift Register, a Address decoder and 8 Data Latches. The analog block
consists of 10 R-2R D/A converters and 10 Operational Amplifier Buffers. For stability consideration,
the power supply and ground lines are separate between the digital block and the operational amplifier
buffers, and R-2R D/A converters.
LOCK DESCRIPTIONB
SHIEFT RGISTER
The AA88368AP has a 14 bits shift register to store 14 bits anytime. At the rising edge of CLK signal,
the external digital data will be shifted into the LSB of the Shift-Register. And the original contents in
the Shift Register will also shift right. The 14^th bit(MSB) will also output to DO for cascade application
for this device. Figure 4 shows the configuration.
ADRESS DECODER and DATA LATCH
When the LD pin is on high then the 14 bits stored in the shift register will be latched. The 4 upper bits
(addr-bit) will send to address decoder to select one of the ten Data Latches. The 10 lower bits(data-bit)
will be written into the indicated Data-Latch as the internal digital data.
R-2R D/A CONVERTER
The internal digital data from the Data Latch will be transferred into a analog DC voltage with 8-bit
resolution by R-2R D/A converter in a max.20us settling time.
OPERATIONAL AMPLIFIER BUFFER
Each channel has a corresponding operational amplifier output buffer. It’s used to get a complete
monotonic analog DC output and provide a high current drive /sink capability up to 2mA. It could
operate in the full range from VCC to GND as the analog power is equal to the system power.
DEVICE OPERATION
Figure 5 shows the input/output timing. A 14-bit address/data is serially input into the shift register
through the DI pin synchronously at the rising edge of the CLK signal. The format of the shift register
is shown in the Figure 6.The lower 10 bits (D0 ~ D9) are data bits to be converted, and the upper 4
bits(D10 ~ D13) are address bits to select a channel to be written. As the LD pin is on high, the address
decoder load the upper 4 bits to select a Data-Latch, and write the 10 data bits into it. Figure 7 shows
the Data-Latch address map, and Table2 shows the address decoding. 8 data bits written into individual
Data-Latch are converted into analog DC voltage through R-2R resistor ladder, dividing the supply
voltage |VDD-VSS| in 10-bit resolution. Output buffers at individual D/A converter outputs can rise up
7
2006/7/5