UT8SF2M40 Datasheet, PDF (7/23 Pages) Aeroflex Circuit Technology – UT8SF2M40 80Megabit Flow-thru SSRAM

Changing Clock Frequencies
The CLK input frequency should be established at a power on,
and may only be changed while in SLEEP mode (reference
Table 6).
External Connections
A precision 25kohm < +0.2% low TCR < 25ppm/^oC resistor is
required to be connected between device pin EXTRES (R15)
and V_SS.
In order to ensure proper operation in conjunction with JTAG
boundary scan (reference applications note MEM-AN-005),
Aeroflex requires that specific package pins be biased through
soft connections to either V_DDQ or V_SSQ. Table 5 is a list of
these required external biases.
Table 5. External Bias Conditions
Signal Name
NUIL¹
NUIH²
TDO
TCK
Package Pin
H1, H20, N1, N2,
N19, N20, P13,
R7, R8, R10, R12,
R13, R14, R16
P16, R8
R5
R9
DQ[47:0]³
ref Table 7
Bias Condition
>10kΩ to V_SSQ
>10kΩ to V_DDQ
>10kΩ to V_DDQ
>10kΩ to V_SSQ
>10kΩ to V_DDQ or
V_SSQ
Notes:
1. NUIL = Not Used Input Low
2. NUIH = Not Used Input High
3. Aeroflex recommends connecting all DQ[47:0] to either V_DDQ or V_SSQ
through >10kΩ resistors.
Operation
Standby Mode
Continue Deselect
Read Cycle (Start Burst)
Read Cycle (Cont. Burst)
NOP/Dummy Read
(Start)
NOP/Dummy Read
(Cont.)
Write Cycle (Start Burst)
Write Cycle (Cont. Burst)
Dummy Write (Start)
Dummy Write (Cont.
Burst)
Clock Inhibit (Stall)
Sleep Mode
Shutdown Mode
Table 6: Truth Table for UT8SF2M40^{[1,2,3,4,5,6,7]}
Address
Used
CSx*
ZZ
SHUT
DOWN
ADV_LD
WE
BWEx
None
HL
L
L
X
X
None
XL
L
H
X
X
External
LL
L
L
H
X
Next
XL
L
H
X
X
External
LL
L
L
H
X
OE CEN CLK DQs
X L L-H 3-State
X L L-H 3-State
L L L-H Data Out
L L L-H Data Out
H L L-H 3-State
Next
XL
L
H
X
X
H L L-H 3-State
External
LL
L
Next
XL
L
None
LL
L
Next
XL
L
L
L
L
X L L-H Data In
H
X
L
X L L-H Data In
L
L
H
X L L-H 3-State
H
X
H
X L L-H 3-State
N/A
N/A
None
XL
L
HH
L
XX
H
X
X
X
X H L-H N/A
X
X
X
X X X 3-State
X
X
X
X X X 3-State
Notes:
* All chip selects active when L, at least one chip select inactive when H
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW.
2. Write is defined by WE and BWEx
3. When a Write cycle is detected, all I/Os are tri-stated.
4. The DQ pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally
during Write cycles. During a Read cycle DQs = tri-state when OE is inactive or when
the device is deselected and DQs = data when OE is active.
36-00-01-005
Ver. 1.0.0
7
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