UT54ACS165E Datasheet, PDF (6/9 Pages) Aeroflex Circuit Technology – 8-Bit Parallel Shift Registers

SYMBOL
PARAMETER
CONDITION
V_DD
MINIMUM MAXIMUM UNIT
f_MAX
Maximum clock frequency
C_L = 50pF 3.0V, 4.5V, and
5.5V
71
MHz
t_SU1
SER, SH/LD, CLKINH or CLK C_L = 50pF 3.0V, 4.5V, and
7
ns
Setup time before CLK↑ or
5.5V
CLKINH↑
t_SU2
Data setup time before SH/LD C_L = 50pF 3.0V, 4.5V, and
7
ns
5.5V
t_H1
SER hold time after CLK or
C_L = 50pF 3.0V, 4.5V, and
2
ns
CLKINH↑
5.5V
t_H2
CLKINH↑ hold time after CLK
C_L = 50pF
3.0V, 4.5V, and
5.5V
2
ns
t_H33
Hold time for any input after
SH/LD
C_L = 50pF 3.0V, 4.5V, and
5.5V
2
ns
t_W
Minimum pulse width
C_L = 50pF 3.0V, 4.5V, and
7
ns
CLK or CLKINH high
5.5V
CLK or CLKINH low
SH/LD
Notes:
1. Maximum allowable relative shift equals 50mV.
2. All specifications valid for radiation dose ≤ 1E6 rads(Si) per MIL-STD-883 Method 1019 Condition A and section 3.11.2.
3. Based on characterization, hold time (t_H3) of 0ns for data pins A-H, can be assumed if data setup time (t_SU2) is >10ns. This is guaranteed, but not tested.
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