9Q512K32 Datasheet, PDF (3/14 Pages) Aeroflex Circuit Technology – UT9Q512K32 16Megabit SRAM MCM

WRITE CYCLE
A combination of Wn less than V_IL(max) and En less than
V_IL(max) defines a write cycle. The state of G is a “don’t care”
for a write cycle. The outputs are placed in the high-impedance
state when eitherG is greater than V _IH(min), or when Wn is less
than V_IL(max).
Write Cycle 1, the Write Enable-controlled Access is defined
by a write terminated by Wn going high, with En still active.
The write pulse width is defined by t_WLWH when the write is
initiated byWn, and by t_ETWH when the write is initiated byEn.
Unless the outputs have been previously placed in the high-
impedance state byG, the user must wait t _WLQZ before applying
data to the nine bidirectional pins DQ(7:0) to avoid bus
contention.
Write Cycle 2, the Chip Enable-controlled Access is defined by
a write terminated by the latter of En going inactive. The write
pulse width is defined by t_WLEF when the write is initiated by
Wn, and by t_ETEF when the write is initiated by the En going
active. For the Wn initiated write, unless the outputs have been
previously placed in the high-impedance state by G, the user
must wait t_WLQZ before applying data to the eight bidirectional
pins DQ(7:0) to avoid bus contention.
TYPICAL RADIATION HARDNESS
The UT9Q512K32 SRAM incorporates features which allows
operation in a limited radiation environment.
Table 2. Radiation Hardness
Design Specifications¹
Total Dose 50
krad(Si)
Heavy Ion
Error Rate²
<1E-8
Errors/Bit-Day
Notes:
1. The SRAM will not latchup during radiation exposure under recommended
operating conditions.
2. 90% worst case particle environment, Geosynchronous orbit, 100 mils of
Aluminum.
3