UT700 Datasheet, PDF (29/46 Pages) Aeroflex Circuit Technology – UT700 32-bit Fault-Tolerant SPARCTM V8/LEON 3FT Processor

4.2 Output Timing Characteristics for Memory Interface, ERROR, and WDOG
(V_DD = 3.3V + 0.3V; V_DDC = 1.2V + 0.1V; T_C = -55^oC to 105^oC)
Symbol
Description
Min
t1a^{1 SDCLK↑ to ADDR[27:0] valid}
1.5
t1b^{1 SDCLK↑ to SDCS[1:0] valid}
2
t1c^{1 SDCLK↑ to output valid}
1.5
SDRAS, SDCAS, and SDWE
t1d^{1 SDCLK↑ to SDDQM[3:0] valid}
2.5
t1e^{1 SDCLK↑ to output valid}
1
(WRITE, OE, IOS, ROMS[1:0], RWE [3:0], RAMOE [4:0],
RAMS[4:0], and READ)
t2^{1,2 SDCLK↑ to output valid}
2.5
(DATA[31:0] and CB[15:0])
t3^{1,2,3 SDCLK↑ to output high-Z}
2.5
(DATA[31:0] and CB[15:0])
t4^{1 SDCLK↑ to signal low}
--
(ERROR and WDOG⁴)
t8^{1,2,3 WRITE↑ or RWE[3:0]↑ to output high-z}
0.5
(DATA [31:0] and CB[15:0])
t9^{1 Skew from first memory output signal transition to last memory output}
--
signal transition
Notes:
1. All outputs are measured using the load conditions shown in Figure 17.
2. CB[7] is not tested in the case of BCH EDAC.
3. High-Z defined as +/-300mV change from steady state.
4. Guaranteed by design.
Max
Units
8.5
ns
7.5
ns
8.5
ns
8.5
ns
8
ns
8.5
ns
8.5
ns
10
ns
--
ns
2
ns
36-00-00-000
Ver. 1.3.1
29
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