UT80C196 Datasheet, PDF (26/42 Pages) Aeroflex Circuit Technology – UT80C196KD Microcontroller

5.0 AC CHARACTERISTICS READ CYCLE
(V_DD = 5.0V ±10%) (T_C = -55°C to +125°C for "C" screening and -40°C to +125°C for "W" screening)
SYMBOL
PARAMETER
MINIMUM
MAXIMUM
t_AVYV5
Address VALID to READY setup
2T _OSC - 30
t_YLYH5
Non-READY time
No upper limit
t_CLYX1,5
READY hold after CLKOUT low
0
2T _OSC - 20
t_LLYX1,5
READY hold after ALE low
T_OSC
3T _OSC - 20
t_AVGV5
Address valid to BUSWIDTH setup
2T _OSC - 30
t_CLGX5
BUSWIDTH hold after CLKOUT low
0
t_AVDV2,5
Address valid to input data valid
3T _OSC - 29
t_RLDV2
RD Active to input data valid
5 (see Note 5)
T_OSC - 26
t_CLDV5
CLKOUT low to input data valid
5
T_OSC - 26
t_RHDZ5
End of RD to input data float
0
T_OSC -10
t_RXD
5
X
Data hold after RD inactive
0
T_OSC -10
f_OSC5
Frequency on XTAL1
1 (see Note 7) 20 (see Note 6)
T_OSC5
XTAL1 period (1/f_OSC)
50 (see Note 6) 1000 (see Note 7)
t_XHCH
XTAL1 high to CLKOUT high or low
0
+25
t_CLCL ⁶
CLKOUT cycle time
2T_OSC Typical
t_CHCL ⁵
CLKOUT high period
T_OSC - 10
T_OSC +10
t_CLLH
CLKOUT falling edge to ALE rising
-5
+15
t_LLCH5
ALE falling edge to CLKOUT rising
-10
+10
t_LHLH2, ⁶
ALE cycle time
4T_OSC Typical
t_LHLL ⁵
ALE high period
T_OSC - 10
T_OSC +15
t_AVLL5
Address setup to ALE falling edge
T_OSC - 15
t_LLAX
Address hold after ALE falling edge
T_OSC - 20
T_OSC +5
t_LLRL
ALE falling edge to RD falling edge
T_OSC - 5
T_OSC +10
t_RLCL
RD low to CLKOUT falling edge
-5
+10
t_RLRH2
RD low period
T_OSC - 5
t_RHLH3,5
RD rising edge to ALE rising edge
T_OSC-10
T_OSC +10
t_RLA
5
Z
RD low to address float
-5
+5
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Mhz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns