UT699E Datasheet, PDF (17/41 Pages) Aeroflex Circuit Technology – UT699E 32-bit Fault-Tolerant SPARCTM V8/LEON 3FT Processor

3.2 Recommended Operating Conditions
(V_DD = 3.3V + 0.3V; V_DDC = 1.2V + 0.1V; T_C = -55^oC to 105^oC)
Symbol
Description
Min
V_DDC
Core supply voltage
1.1
V_DD
I/O supply voltage
3.0
V_IN
Input voltage any pin
0
T_C
Case operating temperature
-55
t_R
Rise time, all CMOS and PCI inputs
--
(0.1V_DD to 0.9V_DD)
t_F
Fall time, all CMOS and PCI inputs
--
(0.9V_DD to 0.1V_DD)
3.3 Operational Environmet
The UT699E processor includes the following SEU mitigation features:
* Cache memory error-detection of up to 4 errors per tag or 32-bit word
* Autonomous and software transparent error handling
* No timing impact due to error detection or correction
Max
1.3
3.6
V_DD
105
20
Units
V
V
V
o_C
ns
20
ns
PARAMETER
Total Ionizing Dose (TID) ¹
Single Event Latchup Immune (SEL) ²
Single Event Upset (SEU) ^{3, 4}
Inherent register upset rate
Single Event Upset (SEU) ^{3, 4}
Multiple-bit error (MBE) rate which over-
comes internal error detection & correction
architecture
LIMIT
1E5
<110
5.2E-7
2.8E-11
UNITS
rad (Si)
MeV-cm²/mg
errors/device-day
MBE/device-day
Notes:
1. TID irradation per MIL-STD-883, Test Method 1019, condition A. Post irradiation electrical testing performed at room temperature.
2. Worst case temperature and voltage of T_C = +105^oC, V_DD = 3.6V, V_DDC = 1.3V.
3. Contact factory for error rate information.
4. The error rate calculation was performed using SpaceRad 6.0 for a Geosynchronous orbit in the Adams 90% worst-case environment with 100mil Al
shielding.
36-00-00-001
Ver. 1.5.0
17
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