UT8SF2M32 Datasheet, PDF (1/27 Pages) Aeroflex Circuit Technology – UT8SF2M32 64Megabit Flow-thru SSRAM

Standard Products
UT8SF2M32 64Megabit Flow-thru SSRAM
Preliminary Datasheet
www.aeroflex.com/memories
April 2015
FEATURES
 Synchronous SRAM organized as 2Meg words x 32bit
 Continuous Data Transfer (CDT) architecture eliminates
wait states between read and write operations
 Supports 40MHz to 80MHz bus operations
 Internally self-timed output buffer control eliminates the
need for synchronous output enable
 Registered inputs for flow-thru operations
 Single 2.5V to 3.3V supply
 Clock-to-output times
- Clk to Q = 12ns
 Clock Enable (CEN) pin to enable clock and suspend
operation
 Synchronous self-timed writes
 Three Chip Enables (CS0, CS1, CS2) for simple depth
expansion
 "ZZ" Sleep Mode option for partial power-down
 "SHUTDOWN" Mode option for deep power-down
 Four Word Burst Capability--linear or interleaved
 Operational Environment
- Total Dose: 100 krad(Si)
- SEL Immune: ≤ 100MeV-cm²/mg
- SEU error rate: 1 x 10 ^-15errors/bit-day
with internal error correction
 Package options:
- 288-lead CLGA, CCGA, and CBGA
 Standard Microelectronics Drawing (SMD) 5962-15214
- QMLQ and Q+ pending
INTRODUCTION
The UT8SF2M32 is a high performance 67,108,864-bit
synchronous static random access memory (SSRAM) device
that is organized as 2M words of 32 bits. This device is
equipped with three chip selects (CS0, CS1, and CS2), a write
enable (WE), and an output enable (OE) pin, allowing for
significant design flexibility without bus contention. The
device supports a four word burst function using (ADV_LD).
The device achieves a very low error rate by employing
SECDED (single error correction double error detection)
EDAC (error detection and correction) scheme during read/
write operations as well as additional autonomous data
scrubbing. The data scrubbing is performed in the background
and is invisible to the user.
All synchronous inputs are registered on the rising edge of the
clock provided the Clock Enable (CEN) input is enabled LOW.
Operations are suspended when CEN is disabled HIGH and the
previous operation is extended. Write operation control signals
are WE and FLSH_PIPE. All write operations are performed
by internal self-timed circuitry.
For easy bank selection, three synchronous Chip Enables
(CS0, CS1, CS2) and an asynchronous Output Enable (OE)
provide for output tri-state control. The output drivers are
synchronously tri-stated during the data portion of a write
sequence to avoid bus contention.
36-00-01-006
Ver. 1.9.4
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