UT8R512K8 Datasheet, PDF (1/23 Pages) Aeroflex Circuit Technology – UT8R512K8 512K x 8 SRAM

Standard Products
UT8R512K8 512K x 8 SRAM
Data Sheet
March 2009
www.aeroflex.com/memories
FEATURES
‰ 15ns maximum access time
‰ Asynchronous operation for compatibility with industry-
standard 512K x 8 SRAMs
‰ CMOS compatible inputs and output levels, three-state
bidirectional data bus
- I/O Voltage 3.3 volts, 1.8 volt core
‰ Operational environment:
- Intrinsic total-dose: 300K rad(Si)
- SEL Immune >100 MeV-cm²/mg
- LET_th (0.25): 53.0 MeV-cm²/mg
- Memory Cell Saturated Cross Section 1.67E-7cm²/bit
- Neutron Fluence: 3.0E14n/cm²
- Dose Rate
- Upset 1.0E9 rad(Si)/sec
- Latchup >1.0E11 rad(Si)/sec
‰ Packaging options:
- 36-lead ceramic flatpack (3.762 grams)
‰ Standard Microcircuit Drawing 5962-03235
- QML Q & Vcompliant part
INTRODUCTION
The UT8R512K8 is a high-performance CMOS static RAM
organized as 524,288 words by 8 bits. Easy memory expansion
is provided by active LOW and HIGH chip enables (E1, E2), an
active LOW output enable (G), and three-state drivers. This
device has a power-down feature that reduces power
consumption by more than 90% when deselected.
Writing to the device is accomplished by taking chip enable one
(E1) input LOW, chip enable two (E2) HIGH and write enable
(W) input LOW. Data on the eight I/O pins (DQ0 through DQ7)
is then written into the location specified on the address pins
(A0 through A18). Reading from the device is accomplished by
taking chip enable one (E1) and output enable (G) LOW while
forcing write enable (W) and chip enable two (E2) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins will appear on the I/O pins.
The eight input/output pins (DQ0 through DQ7) are placed in a
high impedance state when the device is deselected (E1 HIGH
or E2 LOW), the outputs are disabled (G HIGH), or during a
write operation (E1 LOW, E2 HIGH and W LOW).
A(18:0)
E1
E2
G
W
INPUT
DRIVER
INPUT
DRIVERS
TOP/BOTTOM
DECODER
BLOCK
DECODER
INPUT
DRIVERS
ROW
DECODER
MEMORY
ARRAY
INPUT
DRIVERS
COLUMN
DECODER
COLUMN
I/O
DATA
WRITE
CIRCUIT
INPUT
DRIVERS
CHIP ENABLE
OUTPUT ENABLE
DATA
READ
CIRCUIT
OUTPUT
DRIVERS
WRITE ENABLE
Figure 1. UT8R512K8 SRAM Block Diagram
1
DQ(7:0)