UT54ACTS899 Datasheet, PDF (1/17 Pages) Aeroflex Circuit Technology – 9-bit Latchable Transceiver with Parity Generator/Checker

Standard Products
UT54ACTS899
9-bit Latchable Transceiver with Parity Generator/Checker
Datasheet
May 16, 2012
www.aeroflex.com/Logic
FEATURES
 Latchable transceiver with output source/sink of 24mA
 Option to select generate parity and check or "feed-through"
data/parity in directions A-to-B or B-to-A
 Independent latch enable for A-to-B and B-to-A directions
 Select pin for ODD/EVEN parity
 ERRA and ERRB output pins for parity checking
 Ability to simultaneously generate and check parity
 m Commercial CMOS
 Operational environment:
- Total dose: 100K rad(Si)
- Single Event Latchup immune
- SEU immune
 Standard Microcircuit Drawing 5962-06240
- QML compliant part
 Package:
- 28-pin ceramic flatpack
DESCRIPTION
The UT54ACTS899 is a 9-bit to 9-bit parity transceiver with
transparent latches. The device can operate as a feed-through
transceiver or it can generate/check parity from the 8-bit data
busses in either direction. The UT54ACTS899 features inde-
pendent latch enables for the A-to-B direction and the B-to-A
direction, a select pin for ODD/EVEN parity, and separate
error signal output pins for checking parity.
PIN DESCRIPTION
Inputs
A0-A7
B0-B7
APAR, BPAR
ODD/EVEN
GBA, GAB
SEL
LEA, LEB
ERRA, ERRB
Outputs
A Bus Data Inputs/Data Outputs
B Bus Data Inputs/Data Outputs
A and B Bus Parity Inputs
ODD/EVEN Parity Select, Active LOW for
EVEN Parity
Output Enables for A or B Bus, Active Low
Select Pin for Feed-through or Generate
Mode, LOW for Generate Mode
Latch Enables for A and B Latches, HIGH
for Transparent Mode
Error Signals for Checking Generated Par-
ity with Parity In, LOW if Error Occurs
28-Lead Flatpack
Pinout
ODD/EVEN
ERRA
LEA
A0
A1
A2
A3
A4
A5
A6
A7
APAR
GBA
VSS
1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 21
9 20
10 19
11 18
12 17
13 16
14 15
VDD
GAB
B0
B1
B2
B3
B4
B5
B6
B7
BPAR
LEB
SEL
ERRB
1