UT54ACTS74E Datasheet, PDF (1/9 Pages) Aeroflex Circuit Technology – Dual D Flip-Flops with Clear and Preset

UT54ACTS74E
Dual D Flip-Flops with Clear & Preset
July, 2013
Datasheet
www.aeroflex.com/Logic
FEATURES
• m CRH CMOS process
- Latchup immune
• High speed
• Low power consumption
• Wide power supply operating range from 3.0V to 5.5V
• Available QML Q or V processes
• 14-lead flatpack
• UT54ACTS74E-SMD- 5962-96535
DESCRIPTION
The UT54ACTS74E contains two independent D-type positive
triggered flip-flops. A low level at the Preset or Clear inputs
sets or resets the outputs regardless of the levels of the other
inputs. When Preset and Clear are inactive (high), data at the
D input meeting the setup time requirement is transferred to the
outputs on the positive-going edge of the clock pulse. Follow-
ing the hold time interval, data at the D input may be changed
without affecting the levels at the outputs.
The device is characterized over full HiRel temperature range
of -55C to +125C.
FUNCTION TABLE
PRE
L
H
L
H
H
H
INPUTS
CLR
CLK
H
X
L
X
L
X
H

H

H
L
OUTPUT
D
Q
Q
X
H
L
X
L
H
X
H¹
H¹
H
H
L
L
L
H
X
Q_o
Q_o
Note:
1. The output levels in this configuration are not guaranteed to meet the mini-
mum levels for V_OH if the lows at preset and clear are near V_IL maximum.
In addition, this configuration is nonstable; that is, it will not persist when
either preset or clear returns to its inactive (high) level.
PINOUTS
CLR1
D1
CLK1
PRE1
Q1
Q1
V_SS
14-Lead Flatpack
TopView
1 14
2 13
3 12
4 11
5 10
6
9
7
8
V_DD
CLR2
D2
CLK2
PRE2
Q2
Q2
LOGIC SYMBOL
(4)
PRE1
(3)
CLK1
(2)
D1
(1)
CLR1
(10)
PRE2
(11)
CLK2
(12)
D2
(13)
CLR2
S
C1
D1
R
(5) _Q1
(6) _Q1
(9) _Q2
(8) _Q2
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC
Publication 617-12.
1