UT54ACTS220 Datasheet, PDF (1/12 Pages) List of Unclassifed Manufacturers – Clock and Wait-State Generation Circuit

Standard Products
UT54ACTS220
Clock and Wait-State Generation Circuit
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
‰ 1.2μ CMOS
- Latchup immune
‰ High speed
‰ Low power consumption
‰ Single 5 volt supply
‰ Available QML Q or V processes
‰ Flexible package
- 14-pin DIP
- 14-lead flatpack
‰ UT54ACTS220 - SMD 5962-96753
DESCRIPTION
The UT54ACTS220 is designed to be a companion chip to
UTMC’s UT69151 SμMMIT family for the purpose of gener-
ating clock and wait-state signals. The device contains a divide
by two circuit that accepts TTL input levels and drives CMOS
output buffers. The chip accepts a 48MHz clock and generates
a 24MHz clock. The 48MHz clock can have a duty cycle that
varies by ± 20%. The UT54ACT220 generates a 24MHz clock
with a ± 5% duty cycle variation. The wait-state circuit generates
a single wait-state by delaying the falling edge of DTACK into
the SμMMIT. The clock/timing device generates DTACK from
the falling edge of input RCS which is synchronized by the fall-
ing edge of 24MHz. The SμMMIT drives inputs RCS and
DMACK.
The devices are characterized over full military temperature
range of -55°C to +125°C.
LOGIC SYMBOL
MRST ⁽¹⁰⁾
S
PINOUTS
14-Pin DIP
Top View
NC
1
14
V_DD
CLKOUT ^{2 13} 24MHz
CLKOUT ^{3 12} DTACK
CLKIN ^{4 11}
TEST
NC ^{5 10} MRST
48MHz ⁶
9 _RCS
V_SS
7
8 _DMACK
NC
CLKOUT
CLKOUT
CLKIN
NC
48MHz
V_SS
14-Lead Flatpack
Top View
1 14
2 13
3 12
4 11
5 10
6
9
7
8
V_DD
24MHz
DTACK
TEST
MRST
RCS
DMACK
48MHz ⁽⁶⁾
RCS ⁽⁹⁾
DMACK ⁽⁸⁾
CTR1
SRG2
1D
S
(13)
24MHz
(12)
DTACK
(11)
TEST
(4)
CLKIN
(2)
CLKOUT
(3)
CLKOUT
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC
1
Publication 617-12.