UT54ACS74 Datasheet, PDF (1/10 Pages) List of Unclassifed Manufacturers – Radiation-Hardened Dual D Flip-Flops with Clear & Preset

Standard Products
UT54ACS74/UT54ACTS74
Dual D Flip-Flops with Clear & Preset
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
‰ 1.2μ CMOS
- Latchup immune
‰ High speed
‰ Low power consumption
‰ Single 5 volt supply
‰ Available QML Q or V processes
‰ Flexible package
- 14-pin DIP
- 14-lead flatpack
‰ UT54ACS74 - SMD 5962-96534
‰ UT54ACTS74 - SMD 5962-96535
DESCRIPTION
The UT54ACS74 and the UT54ACTS74 contain two indepen-
dent D-type positive triggered flip-flops. A low level at the
Preset or Clear inputs sets or resets the outputs regardless of the
levels of the other inputs. When Preset and Clear are inactive
(high), data at the D input meeting the setup time requirement
is transferred to the outputs on the positive-going edge of the
clock pulse. Following the hold time interval, data at the D
input may be changed without affecting the levels at the outputs.
The devices are characterized over full military temperature
range of -55°C to +125°C.
FUNCTION TABLE
PRE
L
H
L
H
H
H
INPUTS
CLR
CLK
H
X
L
X
L
X
H
↑
H
↑
H
L
OUTPUT
D
Q
Q
X
H
L
X
L
H
X
H¹
H¹
H
H
L
L
L
H
X
Q_o
Q_o
Note:
1. The output levels in this configuration are not guaranteed to meet the minimum
levels for V_OH if the lows at preset and clear are near V_IL maximum. In
addition, this configuration is nonstable; that is, it will not persist when either
preset or clear returns to its inactive (high) level.
PINOUTS
14-Pin DIP
Top View
CLR1
D1
CLK1
PRE1
Q1
Q1
V_SS
1 14
2 13
3 12
4 11
5 10
6
9
7
8
V_DD
CLR2
D2
CLK2
PRE2
Q2
Q2
14-Lead Flatpack
Top View
CLR1
D1
CLK1
PRE1
Q1
Q1
V_SS
1 14
2 13
3 12
4 11
5 10
6
9
7
8
V_DD
CLR2
D2
CLK2
PRE2
Q2
Q2
LOGIC SYMBOL
(4)
PRE1
(3)
CLK1
(2)
D1
(1)
CLR1
(10)
PRE2
(11)
CLK2
(12)
D2
(13)
CLR2
S
C1
D1
R
(5) _Q1
(6) _Q1
(9) _Q2
(8) _Q2
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC
Publication 617-12.
1