UT54ACS299E Datasheet, PDF (1/14 Pages) Aeroflex Circuit Technology – CMOS 8-bit Universal Shift/Storage Register with Three-State Outputs

Standard Products
UT54ACS299E
CMOS 8-bit Universal Shift/Storage Register with Three-State Outputs
Datasheet
July 2, 2013
www.aeroflex.com/Logic
FEATURES
 Common parallel I/O for reduced pin count
 Additional serial inputs and outputs for expansion
 Three-state outputs for bus-oriented applications
 Operate with outputs enabled or at high impedance
 Four operating modes: shift left, shift right, load and store
 Can be cascaded for n-bit word lengths
 0.6m Commercial RadHard^TM CMOS
- Total dose: 100K rad(Si)
- Single Event Latchup immune
- SEU Onset LET: 95 MeV-cm²/mg (4.5V) and
48MeV-cm²/mg (3.0V)
 Applications:
- Stacked or push-down registers
- Buffer storage
- Accumulator registers
 Output source/sink 24mA
 Available QML Q or V processes
 Standard Microcircuit Drawing 5962-06238
 Package:
- 20-lead flatpack
DESCRIPTION
The UT54ACS299E 8-bit shift/storage register is built using
Aeroflex’s Commercial RadHard^TM epitaxial CMOS technolo-
gy and is ideal for space applications. The UT54ACS299E is an
8-bit universal shift/storage register featuring multiplexed I/O
ports to achieve full 8-bit data handling in a single 20-pin pack-
age. Two function-select (S0, S1) inputs and two output enable
(OE1, OE2) inputs can be used to choose the mode of operation
listed in the function table. Additional outputs are provided for
flip flops Q0, Q7 to allow easy serial cascading. A separate
active low master reset (MR) is used to reset the register, over-
riding the select and CP inputs. All flip-flops are brought out
through three-state buffers to separate I/O pins that also serve
as data inputs in the parallel load mode. All other state changes
are initiated by the rising edge of the clock.
LOGIC SYMBOL
MR ₍₉₎
OE1 ₍₂₎
OE2 ₍₃₎
S0 (1)
S1 ⁽¹⁹⁾
CP ⁽¹²⁾
R
SRG8
&
3EN13
0
1
M
0
3
C4/1 /2
DS0 ⁽¹¹⁾
I00 (7)
I01 ₍₁₃₎
I02 (6)
I03 (14)
I04 (5)
I05 (15)
I06 (4)
I07 (16)
DS7 ⁽¹⁸⁾
1, 4D
3, 4D
5, 13
Z5
3, 4D
6, 13
Z6
(8)
Q0
3, 4D
12, 13
Z12
2, 4D
(17)
Q7
PIN DESCRIPTION
Pin Names
Description
CP
Clock Pulse Input
DS0
Serial Data Input for Right Shift
DS7
Serial Data Input for Left Shift
S0, S1 Mode Select Inputs
MR
Asynchronous Master Reset
OE1, OE2 Three-State Output Enable Inputs
IO0-IO7 Parallel Data Inputs or Three-State Parallel Out-
puts
Q0, Q7 Serial Outputs
1