UT54ACS280 Datasheet, PDF (1/10 Pages) Aeroflex Circuit Technology – 9-Bit Parity Generators/Checkers

Standard Products
UT54ACS280/UT54ACTS280
9-Bit Parity Generators/Checkers
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
‰ Generates either odd or even parity for nine data lines
‰ Cascadable for n-bits parity
‰ 1.2μ CMOS
- Latchup immune
‰ High speed
‰ Low power consumption
‰ Single 5 volt supply
‰ Available QML Q or V processes
‰ Flexible package
- 14-pin DIP
- 14-lead flatpack
‰ UT54ACS280 - SMD 5962-96582
‰ UT54ACTS280 - SMD 5962-96583
DESCRIPTION
PINOUTS
14-Pin DIP
Top View
G
1 14
V_DD
H 2 13 F
NC 3 12 E
I 4 11 D
∑ EVEN 5 10 C
∑ ODD 6 9 B
V_SS
7
8
A
14-Lead Flatpack
Top View
The UT54ACS280 and the UT54ACTS280 are 9-bit parity gen-
G
1 14
V_DD
erators/checkers that use high-performance circuitry and fea-
H
2 13
F
tures odd and even outputs to facilitate operation of either odd
NC
3 12
E
or even parity application. The word-length capability is easily
I
4 11
D
expanded by cascading.
∑ EVEN
5 10
C
The devices are characterized over full military temperature
∑ ODD
6
9
B
range of -55°C to +125°C.
V_SS
7
8
A
FUNCTION TABLE
NUMBER OF INPUTS A THRU I
THAT ARE HIGH
OUTPUT
Σ EVEN
Σ ODD
0,2,4,6,8
1,3,5,7,9
H
L
L
H
LOGIC SYMBOL
(8)
A
2k
(9)
B
(10)
C
(11)
D
(12)
E
(13)
F
(1)
G
(2)
H
I ⁽⁴⁾
(5) _∑
EVEN
(6) _∑
ODD
Note:
1
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC
Publication 617-12.