UT54ACS164 Datasheet, PDF (1/10 Pages) Aeroflex Circuit Technology – 8-Bit Shift Registers

Standard Products
UT54ACS164/UT54ACTS164
8-Bit Shift Registers
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
‰ AND-gated (enable/disable) serial inputs
‰ Fully buffered clock and serial inputs
‰ Direct clear
‰ 1.2μ CMOS
- Latchup immune
‰ High speed
‰ Low power consumption
‰ Single 5 volt supply
‰ Available QML Q or V processes
‰ Flexible package
- 14-pin DIP
- 14-lead flatpack
‰ UT54ACS164 - SMD 5962-96556
‰ UT54ACTS164 - SMD 5962-96557
DESCRIPTION
The UT54ACS164 and the UT54ACTS164 are 8-bit shift reg-
isters which feature AND-gated serial inputs and an asynchro-
nous clear. The gated serial inputs (A and B) permit complete
control over incoming data. A low at either input inhibits entry
of new data and resets the first flip-flop to the low level at the
next clock pulse. A high-level at both serial inputs sets the first
flip-flop to the high level at the next clock pulse. Data at the
serial inputs may be changed while the clock is high or low,
providing the minimum setup time requirements are met. Clock-
ing occurs on the low-to-high-level transition of the clock input.
The devices are characterized over full military temperature
range of -55°C to +125°C.
FUNCTION TABLE
INPUTS
OUTPUTS
CLR CLK
A
L
X
X
B
Q_A
Q_{B ...} Q_H
X
L
L
L
H
L
X
X
Q_A0
Q_B0
Q_H0
H
↑
H
H
H
Q_An
Q_Gn
H
↑
L
X
L
Q_An
Q_Gn
H
↑
X
L
L
Q_An
Q_Gn
PINOUTS
A
B
Q_A
Q_B
Q_C
Q_D
V_SS
14-Pin DIP
Top View
A
1
14
V_DD
B
2
13
Q_H
Q_A
3
12
Q_G
Q_B
4
11
Q_F
Q_C
5
10
Q_E
Q_D
6
V_SS
7
9 CLR
8 CLK
14-Lead Flatpack
Top View
1 14
2 13
3 12
4 11
5 10
6
9
7
8
V_DD
Q_H
Q_G
Q_F
Q_E
CLR
CLK
LOGIC SYMBOL
(9)
CLR
(8)
CLK
A ⁽¹⁾
(2)
B
SRG8
R
C1/
&
1D
(3)
Q_A
(4)
(5) ^QB
(6) ^QC
(10) ^QD
(11) ^QE
(12) ^QF
(13) ^QG
Q_H
Notes:
1. Q_A0, Q_B0, Q_H0 = the level of Q_A, Q_B or Q_H, respectively, before the indicated
steady-state input conditions were established.
2. Q_An and Q_Gn = the level of Q_A or Q_G before the most recent ↑ transition of
the clock; indicates a one-bit shift.
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
1