UT54ACS109E Datasheet, PDF (1/10 Pages) Aeroflex Circuit Technology – Dual J-K Flip-Flops

UT54ACS109E
Dual J-K Flip-Flops
Septenber 2010
www.aeroflex.com/Logic
FEATURES
• 0.6μm CRH CMOS Process
- Latchup immune
• High speed
• Low power consumption
• Wide operating power supply of 3.0V to 5.5V
• Available QML Q or V processes
• 16-lead flatpack
DESCRIPTION
The UT54ACS109E is a dual J-K positive triggered flip-flop.
A low level at the preset or clear inputs sets or resets the outputs
regardless of the other input levels. When preset and clear are
inactive (high), data at the J and K input meeting the setup time
requirements are transferred to the outputs on the positive-going
edge of the clock pulse. Following the hold time interval, data
at the J and K input can be changed without affecting the levels
at the outputs. The flip-flops can perform as toggle flip-flops
by grounding K and tying J high. They also can perform as D
flip-flops if J and K are tied together.
The devices are characterized over full HiRel temperature range
of -55°C to +125°C.
FUNCTION TABLE
PRE
L
H
L
H
H
H
H
H
INPUTS
CLR
CLK
H
X
L
X
L
X
H
↑
H
↑
H
↑
H
↑
H
L
OUTPUT
JK Q
Q
XX H
L
XX L
H
X X _H¹ _H¹
LL
L
H
HL
Toggle
L H No Change
HH H
L
X X No Change
Note:
1. The output levels in this configuration are not guaranteed to meet the mini-
mum levels for V_OH if the lows at preset and clear are near V_IL maximum.
In addition, this configuration is nonstable; that is, it will not persist when
either preset or clear returns to its inactive (high) level.
PINOUTS
CLR1
J1
K1
CLK1
PRE1
Q1
Q1
V_SS
16-Lead Flatpack
Top View
1 16
2 15
3 14
4 13
5 12
6 11
7 10
8
9
V_DD
CLR2
J2
K2
CLK2
PRE2
Q2
Q2
LOGIC SYMBOL
(5)
PRE1
(2)
J1
(4)
CLK1
(3)
K1 ₍₁₎
CLR1
S
J1
C1
K1
R
(6) _Q1
(7)
Q1
(11)
PRE2
(14)
J2
(12)
CLK2
(13)
K2
(15)
CLR2
(10)
Q2
(9) _Q2
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and
IEC Publication 617-12.
1