UT130NHBD Datasheet, PDF (1/8 Pages) Aeroflex Circuit Technology – Hardened-by-Design (HBD) Standard Cell

Semicustom Products
UT130nHBD Hardened-by-Design (HBD)
Standard Cell
Advanced Data Sheet
August 2010
www.aeroflex.com/RadHardASIC
FEATURES
‰ Up to 15,000,000 usable equivalent gates using standard
cell architecture
‰ Toggle rates up to 1.5 GHz
‰ Advanced 130nm silicon gate CMOS processed in a
commercial fab
‰ Operating voltage 3.3V I/O and 1.2V core
‰ Multiple product assurance levels to be available in
QML Q and V, military and industrial
‰ Radiation hardened from 100 krads(Si) to 300 krads
(Si) total dose available using Aeroflex Colorado
Springs’s (Aeroflex) RadHard techniques
‰ SEU-immune to less than 1.0x10^-10 errors/bits-day
available using special library cells
‰ Special I/O offering: HSTL, Class I and II, LVDS
‰ Robust Aeroflex Design Library of cells and macros
‰ Support for Verilog and VHDL design languages on Sun
and Linux workstations
‰ Cell models validated in Mentor Graphics® and Synop-
sys^TM design environments
‰ Full complement of industry standard IP cores
‰ Wide selection of SP/DP SRAMs with optional MBIST
and EDAC
‰ Low power dissipation of 18nW/MHz/gate at 1.2V
VDDQ
‰ Operating temperature range of -55oC to +125oC
‰ Package pin count of up to 624 for wire bond and 1248
for Flip-Chip (in development)
PRODUCT DESCRIPTION
The high-performance UT130n HBD Hardened-by-Design
ASIC standard cell family features densities up to
15,000,000 equivalent gates and will be available in multi-
ple quality assurance levels such as MIL-PRF-38535, QML
V and Q, military, industrial grades and non-RadHard
versions.
For those designs requiring stringent radiation hardness,
Aeroflex's 130nm process employs a special technique that
enhances the total dose radiation hardness to 300 krads(Si)
while maintaining circuit density and reliability. In addition,
the process uses epitaxial wafers for greater transient radi-
ation hardness and latch-up immunity.
The UT130nHBD ASIC family uses highly efficient stan-
dard cell architecture for internal cell instantiation
developed using Aeroflex's patented architectures. Com-
bined with state-of-the-art, timing driven placement and
routing tools, the area utilization and signal routing of tran-
sistors is maximized using six metal interconnect routing
layers. Table 1, 2 and 3 summarizes some of the most im-
portant aspects of the 130nm ASIC Library.
The UT130nHBD ASIC family is supported by an extensive
cell library that includes standard logic functions, Phase
Lock Loop (PLL) and SRAM with optional MBIST and
EDAC. Aeroflex's IP library includes the following
functions:
• Intel 80C31® equivalent
• Intel 80C196® equivalent
• MIL-STD-1553 functions (BRCTM, RTI, RTMP)
• MIL-STD-1750 microprocessor
• RISC microcontroller
• Aeroflex Gaisler - LEON3 and other IP can be reviewed
at www.gaisler.com
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