UT01VS50D Datasheet, PDF (1/14 Pages) Aeroflex Circuit Technology – UT01VS50D Voltage Supervisor

Standard Products
UT01VS50D Voltage Supervisor
Data Sheet
July 28, 2014
www.aeroflex.com/voltsupv
FEATURES
 4.75V to 5.5V Operating voltage range
 Power supply (V_DD) monitor set by the internal voltage
reference at 4.65V
 Precision Input Voltage Monitor using an internal 1.25V
voltage reference
 Watchdog Timer Circuit monitoring activity on WDI input
- Nominal timeout 1.6s
 RESET_OD output responding to the V_DD monitor and the
manual reset input MR
- Nominal RESET_OD pulse width 200ms
 RESET_OD level valid for V_DD>=1.2V
 Operating Temperature Range -55^oC to +125^oC
 Low Power, Typical 400uA
 Operational environment:
- Total dose: 300 krad(Si)
- SEL Immune: <110 MeV-cm²/mg @125^oC
- SET Immune: <80 MeV-cm²/mg
 Packaging options:
- 8-lead dual-in-line flatpack
 Standard Microelectronics Drawing (SMD) 5962-11213
- QML Q and V
INTRODUCTION
The UT01VS50D’s function is to monitor vital supply and signal
voltages in microprocessor systems. It provides for safe reset
during power up, power down and brownout conditions by using
an internal precision voltage reference.
The UT01VS50D monitors activity at an independent watchdog
input by employing an internal timer and a watchdog output that
goes low if the input is not toggled within 1.6s. It provides for
precision voltage threshold detection on an independent voltage
input which could be used for battery or supply-low monitoring
of a supply voltage other than V_DD.
The UT01VS50D includes an active low manual reset with an
open drain output.
APPLICATIONS
 Voltage Supervisor function for various systems including
microprocessors, microcontrollers, DSPs and FPGAs
 Critical battery and power supply monitoring
 Replacement of older discrete solutions to improve reliability,
accuracy and reduce complexity of the systems
MR
RESET &
DIGITAL CONTROL
VDD
+
-
WDI TIMER
4.65 V
GND
VREF
1.25 V
WDI TRANSITION
DETECTOR
OSC
-
PFI
+
WDO
RESET_OD
WDI
PFO
Figure 1. UT01VS50D Functional Block Diagram
1