UT0.25UHBD Datasheet, PDF (1/13 Pages) Aeroflex Circuit Technology – Hardened-by-Design Standard Cell ASIC

Semicustom Products
UT0.25μHBD Hardened-by-Design Standard Cell ASIC
Data Sheet
June 2010
www.aeroflex.com/RadHardASIC
FEATURES
‰ Up to 3,000,000 usable equivalent gates using standard
cell architecture
‰ Toggle rates up to 1.2 GHz
‰ Advanced 0.25μ silicon gate CMOS processed in a com-
mercial fab
‰ Operating voltage of 100% 3.3V or 3.3V I/O and 2.5V
core
‰ Input buffers are 5-volt tolerant
‰ Multiple product assurance levels available, QML V
and Q, military, industrial
‰ Radiation hardened from 100 krads(Si) to 1 Mrad total
dose available using Aeroflex’s RadHard techniques
‰ SEU-immune to less than 1.0E-10 errors/bits-day avail-
able using special library cells
‰ Robust Aeroflex Design Library of cells and macros
‰ Support for Verilog and VHDL design languages on Sun
and Linux workstations
‰ Cell models validated in Mentor Graphics® and Synop-
sys^TM design environments
‰ Full complement of industry standard IP cores
‰ Various RAM configurations available
‰ Supports cold sparing for power down applications
‰ Power dissipation of 0.04μW/MHz/gate at V_DDCORE
2.5V and 20% duty cycle and 0.06μW/MHz/gate at
V_DDCORE 3.3V and 20% duty cycle
‰ External chip capacitor attachment option available to
space quality levels (for improved SSO response)
PRODUCT DESCRIPTION
The high-performance UT0.25um Hardened-by-Design
ASIC standard cell family features densities up to 3,000,000
equivalent gates and is available in multiple quality assur-
ance levels such as MIL-PRF-38535, QML V and Q,
military, industrial grades, and non-RadHard versions.
For those designs requiring stringent radiation hardness,
Aeroflex's 0.25um process employs a special technique that
enhances the total dose radiation hardness from
100Krads(Si) to 1 Mrad while maintaining circuit density
and reliability. In addition, for greater transient radiation
hardness and latch-up immunity, the deep submicron pro-
cess is built on epitaxial wafers.
Developed from Aeroflex's patented architectures, the
0.25um ASIC family uses a highly efficient standard cell
architecture for internal cell instantiation. Combined with
state-of-the-art, timing driven placement and routing tools,
the area utilization and signal routing of transistors is max-
imized using five levels of metal interconnect.
The UT0.25uHBD ASIC family is supported by an exten-
sive cell library that includes SSI, MSI, and 54XX
equivalent functions, as well as PLL, RAM, and cores. Aer-
oflex's core library includes the following functions:
• Intel 80C31® equivalent
• Intel 80C196® equivalent
• MIL-STD-1553 functions (BRCTM, RTI, RTMP)
• MIL-STD-1750 microprocessor
• RISC microcontroller
• Select RAM configurations (with optional MBIST and
EDAC)
• Phase Locked Loop (PLL)
• Aeroflex Gaisler - LEON3 and other IP can be reviewed
at www.gaisler.com/CMS
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