EVA-X4150 Datasheet, PDF (1/2 Pages) Advantech Co., Ltd. – Cost-Effective x86 SoC for Industrial Embedded Platforms

EVA-X4150
Cost-Effective x86 SoC for
Industrial Embedded Platforms
Features
 32-bit 486SX instruction set compatible SoC
 Operating frequency up to 150 MHz
 System memory: 32/64/128 MB SDRAM
 Integrated interfaces: PCI, ISA, IDE, Ethernet MAC, USB, SPI, I2C and LPC
 Supports up to 40-bit GPIO and 5 UART port addresses
 Supports dual 10/100 Ethernet MACs
 Low power architecture (fanless, no heatsink required)
 Wide operating temperature (-20° C ~ 85° C)
DOS
Introduction
EVA-X4150 is a fully static 32-bit x86-based processor that powers a wide-range of PC peripherals, applications and OSs, such as DOS, Windows CE, Linux and most popular 32-bit
RTOS (Real Time OS) for maximum software re-use and legacy compatibility. EVA-X4150 integrates comprehensive features and rich I/O flexibility within a single System on Chip, to
reduce board design complexity and shorten product development schedules. Taking advantage of ultra low power consumption, EVA-X4150 is able to operate in wide temperature
range environments without special thermal design, making it the perfect x86-based SoC for diverse embedded applications.
Specifications
Processor Core
Embedded L1 Cache
SDRAM Controller
DMA Controller
Interrupt Controller
Counter / Timer
General Chip Selector
PCI Control Interface
ISA Bus Interface
Ethernet Controller
IDE Controller
Universal Serial Bus
LPC (Low Pin Count) Bus Interface
FIFO UART Port
x86 core, 6 stage pipe-line, 150 MHz
16 KB L1 cache
PC100 / PC133 compliant
Speeds up to 150 MHz
8/16-bit data bus width
Memory space up to 128 MB
Supports DLL for clock phase auto-adjustment
Provides two 82C37 compatible DMA controllers
4-channel 8-bit DMA transfer and 3-channel 16-bit DMA transfer
Provides two 8259 compatible interrupt controllers
Independent programmable level/edge-trigger interrupt channels.
Serial IRQ supported
One set 8254 compatible timer controller
Three independent programmable timers / counters
Supports 1 Watch Dog Timer (WDT)
Two set extended Chip Selector
Configurable I/O-map or Memory-map
I/O Addressing: From 2 byte to 64 KB
Memory Address: From 512 byte to 4 GB
32-bit, 33 MHz, compliant with PCI spec. Rev. 2.1
Up to 3 individual PCI master devices
Up to 133 MB/s maximum bandwidth
3.3 V I/O with 5 V tolerance
AT clock programmable
8/16-bit ISA device with Zero-Wait-State
Generate refresh signals to ISA interface during DRAM refresh cycle.
3.3 V I/O with 5 V tolerance
Supports two-port 10/100 Fast Ethernet MAC
IEEE 802.3u MII interface
IEEE 802.3x flow control in full-duplex mode
Descriptor architecture for packet TX/RX
Supports 2 channel Ultra-DMA 100 ( PATA x 4 )
USB 1.1/2.0 Host controller, supports 2 USB ports
Supports HS, FS and LS mode
Supports 3 programmable registers to decode LPC address
Supports up to 5 COM ports
Compatible with 16C550/16C552
COM1 and COM2 support programmable TXD_EN
Supports programmable baud rate generator with the data rate from 50 to 460.8 Kbps
The character options are programmable for 1 start bits; 1, 1.5 or 2 stop bits; even, odd or no parity; 5~8 data bits
Embedded Core Services
All product specifications are subject to change without notice
Last updated : 24-Mar-2009