AD9208 Datasheet, PDF (98/137 Pages) Analog Devices – 14-Bit, 3 GSPS, JESD204B, Dual Analog-to-Digital Converter

Data Sheet
AD9208
Addr. Name
0x0120 SYSREF Control 1
0x0121 SYSREF Control 2
0x0122 SYSREF Control 3
0x0123 SYSREF Control 4
0x0128 SYSREF Status 1
Bits Bit Name
7 Reserved
6 SYSREF± flag reset
5 Reserved
4 SYSREF± transition select
3 CLK± edge select
[2:1] SYSREF± mode select
0 Reserved
[7:4] Reserved
[3:0] SYSREF N-shot ignore
counter select
[7:4] Reserved
[3:2] SYSREF window negative
[1:0] SYSREF window positive
7 Reserved
[6:0] SYSREF± timestamp
delay, Bits[6:0]
[7:4] SYSREF± hold status
[3:0] SYSREF± setup status
Settings
0
1
0
1
0
1
0
1
10
0000
0001
0010
0011
…
1110
1111
00
01
10
11
00
01
10
11
0
1
…
111 1111
Description
Reserved.
Normal flag operation.
SYSREF flags held in reset (setup and hold error flags cleared).
Reserved.
SYSREF is valid on low to high transitions using the selected
CLK± edge. When changing this setting, SYSREF± mode select
must be set to disabled.
SYSREF is valid on high to low transitions using the selected
CLK± edge. When changing this setting, SYSREF± mode select
must be set to disabled.
Captured on the rising edge of CLK± input.
Captured on the falling edge of CLK± input.
Disabled.
Continuous.
N-shot.
Reserved.
Reserved.
Reset Access
0x0 R
0x0 R/W
0x0 R
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R
0x0 R
0x0 R/W
Next SYSREF only (do not ignore).
Ignore the first SYSREF± transition.
Ignore the first two SYSREF± transitions.
Ignore the first three SYSREF± transitions.
…
Ignore the first 14 SYSREF± transitions.
Ignore the first 15 SYSREF± transitions.
Reserved.
0x0 R
Negative skew window (measured in sample clocks). Number 0x0 R/W
of clock cycles before the sample clock by which captured
SYSREF transitions are ignored.
No negative skew; SYSREF must be captured accurately.
One sample clock of negative skew.
Two sample clocks of negative skew.
Three sample clocks of negative skew.
Positive skew window (measured in sample clocks). Number of 0x0 R/W
clock cycles before the sample clock by which captured SYSREF
transitions are ignored.
No positive skew; SYSREF must be captured accurately.
One sample clock of positive skew.
Two sample clocks of positive skew.
Three sample clocks of positive skew.
Reserved.
0x0 R
SYSREF timestamp delay (in converter sample clock cycles). 0x00 R/W
0 sample clock cycle delay.
1 sample clock cycle delay.
…
127 sample clock cycle delay.
SYSREF hold status.
SYSREF setup status.
0x0 R
0x0 R
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