ADF7023BCPZ Datasheet, PDF (93/112 Pages) Analog Devices – High Performance, Low Power, ISM Band FSK/GFSK/OOK/MSK/GMSK Transceiver IC

Data Sheet
Table 70. 0x113: RADIO_CFG_7
Bit Name
[7:6] AGC_LOCK_MODE
[5:4] SYNTH_LUT_CONTROL
[3:0] SYNTH_LUT_CONFIG_1
ADF7023
R/W
Description
R/W
Set to
0: free running
1: manual
2: hold
3: lock after preamble/sync word (only locks on a sync word if PREAMBLE_
MATCH = 0)
R/W
By default, the synthesizer loop bandwidth is automatically selected from
lookup tables (LUT) in ROM memory. A narrow bandwidth is selected in
receive to ensure optimum interference rejection, whereas in transmit, the
bandwidth is selected based on the data rate and modulation settings. For
the majority of applications, these automatically selected PLL loop
bandwidths are optimum. However, in some applications, it may be
necessary to use custom transmit or receive bandwidths, in which case,
various options exist, as follows.
SYNTH_LUT_CONTROL
Description
0
Use predefined transmit and
receive LUTs. The LUTs are
automatically selected from ROM
memory on transitioning into the
PHY_TX or PHY_RX state.
1
Use custom receive LUT based on
SYNTH_ LUT_CONFIG_0 and
SYNTH_LUT_CONFIG_1. In transmit,
the predefined LUT in ROM is used.
2
Use a custom transmit LUT. The
custom transmit LUT must be
written to the 0x10 to 0x18 packet
RAM locations. In receive, the
predefined LUT in ROM is used.
3
Use a custom receive LUT based on
SYNTH_ LUT_CONFIG_0 and
SYNTH_LUT_CONFIG_1, and use a
custom transmit LUT. The custom
transmit LUT must be written to the
0x10 to 0x18 packet RAM locations
Because packet RAM memory is lost in the PHY_SLEEP state, the custom
LUT for transmit must be reloaded to packet RAM after waking from the
PHY_SLEEP state.
R/W
If SYNTH_LUT_CONTROL = 0 or 2, set SYNTH_LUT_CONFIG_1 to 0. If
SYNTH_LUT_CONTROL = 1 or 3, this setting allows the receiver PLL loop
bandwidth to be changed to optimize the receiver local oscillator phase
noise.
Rev. C | Page 93 of 112