ADV7183A_15 Datasheet, PDF (91/104 Pages) Analog Devices – Multiformat SDTV Video Decoder

Table 199. Register 0xB2
Subaddress Register
0xB2
CRC Enable
Write Register
Bit Description
Reserved.
CRC_ENABLE. Enable CRC checksum
decoded from CGMS packet to validate
CGMSD.
Reserved.
ADV7183A
Bit
7 6 5 4 3 2 1 0 Comments
0 0 Set as default
0
Turn off CRC check
1
CGMSD goes high with
valid checksum
00011
Set as default
Table 200. Register 0xC3
Subaddress Register
0xC3
ADC
SWITCH 1
Bit Description
ADC0_SW[3:0]. Manual muxing
control for ADC0.
ADC1_SW[3:0]. Manual muxing
control for ADC1.
Bit
7 6 5 4 3 2 1 0 Comments
Notes
SETADC_sw_man_en = 1
0 0 0 0 No connection
0 0 0 1 AIN1
0 0 1 0 AIN2
0 0 1 1 AIN3
0 1 0 0 AIN4
0 1 0 1 AIN5
0 1 1 0 AIN6
0 1 1 1 No connection
1 0 0 0 No connection
1 0 0 1 AIN7
1 0 1 0 AIN8
1 0 1 1 AIN9
1 1 0 0 AIN10
1 1 0 1 AIN11
1 1 1 0 AIN12
1 1 1 1 No connection
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
No connection
No connection
No connection
AIN3
AIN4
AIN5
AIN6
No connection
No connection
No connection
No connection
AIN9
AIN10
AIN11
AIN12
No connection
Rev. B | Page 91 of 104