ADUM1201_15 Datasheet, PDF (9/28 Pages) Analog Devices – Dual-Channel Digital Isolators

Data Sheet
ADuM1200/ADuM1201
Parameter
25 Mbps (CR Grade Only)
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
For All Models
Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
SWITCHING SPECIFICATIONS
ADuM120xAR
Minimum Pulse Width²
Maximum Data Rate³
Propagation Delay⁴
Pulse Width Distortion, |tPLH − tPHL|⁴
Change vs. Temperature
Propagation Delay Skew⁵
Channel-to-Channel Matching⁶
Output Rise/Fall Time (10% to 90%)
ADuM120xBR
Minimum Pulse Width²
Maximum Data Rate³
Propagation Delay⁴
Pulse Width Distortion, |tPLH − tPHL|⁴
Change vs. Temperature
Propagation Delay Skew⁵
Channel-to-Channel Matching
Codirectional Channels⁶
Opposing Directional Channels⁶
Output Rise/Fall Time (10% to 90%)
5 V/3 V Operation
3 V/5 V Operation
ADuM120xCR
Minimum Pulse Width²
Maximum Data Rate³
Propagation Delay⁴
Pulse Width Distortion, |tPLH − tPHL|⁴
Change vs. Temperature
Propagation Delay Skew⁵
Channel-to-Channel Matching
Codirectional Channels⁶
Opposing Directional Channels⁶
Output Rise/Fall Time (10% to 90%)
5 V/3 V Operation
3 V/5 V Operation
Symbol
Min
Typ
Max
Unit Test Conditions
IDD1 (25)
IDD2 (25)
6.3
8.0
mA
12.5 MHz logic signal freq.
3.4
4.8
mA
12.5 MHz logic signal freq.
3.4
4.8
mA
12.5 MHz logic signal freq.
6.3
8.0
mA
12.5 MHz logic signal freq.
IIA, IIB
VIH
VIL
VOAH, VOBH
VOAL, VOBL
−10
+0.01
+10
μA
0.7 (VDD1 or VDD2)
V
0.3 (VDD1 or VDD2) V
(VDD1 or VDD2) − 0.1 VDD1 or VDD2
V
(VDD1 or VDD2) − 0.5 (VDD1 or VDD2) − 0.2
V
0.0
0.1
V
0.04
0.1
V
0.2
0.4
V
0 V ≤ VIA, VIB ≤ (VDD1 or VDD2)
IOx = −20 μA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 μA, VIx = VIxL
IOx = 400 μA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
CL = 15 pF, CMOS signal levels
PW
1000
ns
1
tPHL, tPLH
50
PWD
Mbps
150
ns
40
ns
11
ps/°C
tPSK
tPSKCD/tPSKOD
tR/tF
PW
50
ns
50
ns
10
ns
CL = 15 pF, CMOS signal levels
100
ns
10
Mbps
tPHL, tPLH
15
55
ns
PWD
3
ns
5
ps/°C
tPSK
22
ns
tPSKCD
tPSKOD
tR/tF
PW
25
tPHL, tPLH
20
PWD
tPSK
3
ns
22
ns
3.0
ns
2.5
ns
CL = 15 pF, CMOS signal levels
20
40
ns
50
Mbps
50
ns
3
ns
5
ps/°C
15
ns
tPSKCD
tPSKOD
tR/tF
3
ns
15
ns
3.0
ns
2.5
ns
Rev. I | Page 9 of 28