AD9984A_15 Datasheet, PDF (9/44 Pages) Analog Devices – High Performance 10-Bit Display Interface

AD9984A
Table 5. Pin Function Descriptions
Mnemonic
Function
RAIN0
Analog Input for the Red
Channel 0
GAIN0
Analog Input for the Green
Channel 0
BBAIN0
Analog Input for the Blue
Channel 0
RAIN1
Analog Input for the Red
Channel 1
GAIN1
Analog Input for the Green
Channel 1
BBAIN1
Analog Input for the Blue
Channel 1
HSYNC0
Horizontal Sync Input
Channel 0
HSYNC1
Horizontal Sync Input
Channel 1
VSYNC0
VSYNC1
SOGIN0
SOGIN1
Vertical Sync Input Channel 0
Vertical Sync Input Channel 1
Sync-on-Green Input
Channel 0
Sync-on-Green Input
Channel 1
CLAMP
External Clamp Input
(Optional)
EXTCK/COAST External Clock (EXTCK)
Optional Coast Input to
Clock Generator (COAST)
PWRDN
REFLO, REFHI
Power-Down Control
(PWRDN)
Input Amplifier Reference
Description
These high impedance inputs accept the red, green, and blue channel graphics signals,
respectively. The three channels are identical and can be used for any colors, but colors
are assigned for convenient reference. They accommodate input signals ranging from
0.5 V to 1.0 V full scale. Signals should be ac-coupled to these pins to support clamp
operation. Refer to Figure 4 and Figure 5.
These inputs receive a logic signal that establishes the horizontal timing reference and
provides the frequency reference for pixel clock generation. The logic sense of these pins
can be automatically determined by the chip or manually controlled by Serial Register 0x12,
Bits[5:4] (Hsync polarity). Only the leading edge of Hsync is used by the PLL; the trailing
edge is used in clamp timing. When Hsync polarity = 0, the falling edge of Hsync is used.
When Hsync polarity = 1, the rising edge is active. These inputs include a Schmitt trigger
for noise immunity.
These inputs for vertical sync provide timing information for generation of the field
(odd/even) and internal coast generation. The logic sense of this pin can be
automatically determined by the chip or manually controlled by Serial Register 0x14,
Bits[5:4] (Vsync polarity).
These inputs help process signals with embedded sync, typically on the green channel.
These pins connect to a high speed comparator with an internally generated threshold.
The threshold level can be programmed in 8 mV steps to any voltage between 8 mV and
256 mV above the negative peak of the input signal. The default voltage threshold is
128 mV. When connected to an ac-coupled graphics signal with embedded sync, a
noninverting digital output is produced on SOGOUT. This output is usually a composite
sync signal, containing both vertical and horizontal sync information that must be
separated before passing the horizontal sync signal for Hsync processing. When not
used, these inputs should be left unconnected. For more details about this function and
how it should be configured, refer to the Sync-on-Green section.
This logic input can be used to define the time during which the input signal is clamped
to ground or midscale. It should be exercised when the reference dc level is known to be
present on the analog input channels, typically during the back porch of the graphics
signal. The CLAMP pin is enabled by setting the control bit clamp function to 1, (Register 0x18,
Bit 4; default is 0). When disabled, this pin is ignored and the clamp timing is determined
internally by counting a delay and duration from the trailing edge of the Hsync input.
The logic sense of this pin can be automatically determined by the chip or controlled by
clamp polarity (Register 0x1B, Bits[7:6]). When not used, this pin can be left unconnected
(there is an internal pull-down resistor) and the clamp function programmed to 0.
This pin has dual functionality.
EXTCK allows the insertion of an external clock source rather than the internally
generated, PLL locked clock. EXTCK is enabled by programming Register 0x03, Bit 2 to 1.
This EXTCK function does not affect the COAST function.
COAST can be used to cause the pixel clock generator to stop synchronizing with Hsync
and continue to produce a clock at its current frequency and phase. This is useful when
processing signals from sources that fail to produce Hsync pulses during the vertical
interval. The coast signal is generally not required for PC-generated signals. The logic
sense of this pin can be determined automatically or controlled by coast polarity
(Register 0x18, Bits[7:6]). When this function and the EXTCK function are not used, this
pin can be grounded and coast polarity programmed to 1. Input coast polarity defaults
to 1 at power-up. This COAST function does not affect the EXTCK function.
PWRDN allows for manual power-down control. If manual power-down control is selected
(Register 0x1E, Bit 4),and this pin is not used, it is recommended to set the pin polarity
(Register 0x1E, Bit 2) to active high and hardwire this pin to ground with a 10 kΩ resistor.
REFLO and REFHI are connected together through a 10 μF capacitor. These are used for
stability in the input ADC circuitry. See Figure 6.
Rev. 0 | Page 9 of 44