AD9912ABCPZ Datasheet, PDF (9/40 Pages) Analog Devices – 1 GSPS Direct Digital Synthesizer with 14-Bit DAC

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD9912
DVDD_I/O 1
DVSS 2
DVDD 3
DVSS 4
DVDD 5
DVSS 6
DVDD 7
DVSS 8
S1 9
S2 10
AVDD 11
NC 12
NC 13
AVDD3 14
NC 15
NC 16
PIN 1
INDICATOR
AD9912
TOP VIEW
(Not to Scale)
48 DAC_RSET
47 AVDD3
46 AVDD3
45 AVDD
44 AVDD
43 AVSS
42 AVDD
41 FDBK_IN
40 FDBK_INB
39 AVSS
38 OUT_CMOS
37 AVDD3
36 AVDD
35 OUT
34 OUTB
33 AVSS
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Input/
Output Pin Type
1
I
Power
2, 4, 6, 8
I
Power
3, 5, 7
I
Power
9, 10, 54, 55
I/O
3.3 V CMOS
11, 19, 23 to 26, I
29, 30, 36, 42, 44,
45, 53
12, 13, 15, 16, 17,
18, 20, 21, 22
14, 46, 47, 49
I
27
I
Power
Power
Differential
input
28
I
Differential
input
31
O
Mnemonic
DVDD_I/O
DVSS
DVDD
S1, S2, S3, S4
AVDD
NC
AVDD3
SYSCLK
SYSCLKB
LOOP_FILTER
Description
I/O Digital Supply.
Digital Ground. Connect to ground.
Digital Supply.
Start-Up Configuration Pins. These pins are configured under program
control and do not have internal pull-up/pull-down resistors.
Analog Supply. Connect to a nominal 1.8 V supply.
No Connect. These unused pins can be left unconnected.
Analog Supply. Connect to a nominal 3.3 V supply.
System Clock Input. The system clock input has internal dc biasing and
should always be ac-coupled, except when using a crystal. Single-ended
1.8 V CMOS can also be used, but it may introduce a spur caused by an input
duty cycle that is not 50%. When using a crystal, tie the CLKMODESEL pin
to AVSS, and connect crystal directly to this pin and Pin 28.
Complementary System Clock. Complementary signal to the input
provided on Pin 27. Use a 0.01 μF capacitor to ground on this pin if the
signal provided on Pin 27 is single-ended.
System Clock Multiplier Loop Filter. When using the frequency multiplier to
drive the system clock, an external loop filter must be constructed and
attached to this pin. This pin should be pulled down to ground with 1 kΩ
resistor when the system clock PLL is bypassed. See Figure 46 for a diagram
of the system clock PLL loop filter.
Rev. F | Page 9 of 40