AD9870 Datasheet, PDF (9/20 Pages) Analog Devices – IF Digitizing Subsystem

AD9870
When the embedded frame sync bit (EFS) is set, FS is either
low or in a high Z state (as determined by the SFST bit), and
framing information is embedded in the data stream. In this
mode, each eight bits of data are surrounded by a start bit (low)
and a stop bit (high), and each frame ends with at least 10 high
bits. Other control bits can be used to invert the frame sync (SFSI),
to delay the frame sync pulse by one clock period (SLFS), to invert
the clock (SCKI), or to set the clock (SCKT) to a high Z state.
Note that if EFS is set, SLFS is a don’t care.
The AD9870 also provides the means for controlling the switch-
ing characteristics of the digital output signals. With a 25 pF
load, the rise and fall times of these signals are no more than
120 ns, 45 ns, 16 ns, or 10 ns if the DS (drive strength) setting
is 0, 1, 2, or 3, respectively.
Table III. SSI Control Registers
Name Width Description
SSICRA (ADDR = 0x18)
AAGC 1
EAGC 1
EFS
1
SFST 1
SFSI
1
SLFS 1
SCKT 1
SCKI 1
Alternate AGC Data Bytes
Embed AGC Data
Embed Frame Sync
Three-State Frame Sync
Invert Frame Sync
Late Frame Sync (1 = Late, 0 = Early)
Three-State CLKOUT
Invert CLKOUT
SSICRB (ADDR = 0x19)
DS
2
FS, CLKOUT, and DOUT Drive
Strength
POWER CONTROL
To allow power consumption to be minimized, the AD9870
possesses numerous SPI-programmable power-down and bias
control bits.
Each major block may be powered down through the appropri-
ate bit of the STBY register. This scheme provides the greatest
flexibility for configuring the IC to a specific application as well
as for tailoring the IC’s power-down and wake-up characteristics.
Table IV summarizes the function of each of the STBY bits.
Note, when all the blocks are in standby, the master reference
circuit is also put into standby and thus the current is reduced
by a further 0.4 mA.
The AD9870 also allows control over the bias current in several
key blocks. The effects on current consumption and system
performance are described in the section dealing with the
affected block.
Table IV. Standby Control Bits
STBY
Bit
Effect
Current
Reduction
(mA)¹
Wake-
Up
Time
(ms)
REF
Voltage Reference Off,
1.5
VREFP, VREFN in
High Z State.
LO
LO Synthesizer Off,
4.8
IOUTL in High Z State.
CKO
Clock Oscillator Off.
0.25
CK
Clock Synthesizer Off,
1.4
IOUTC in High Z State.
Clock Buffer Off if
ADC Is Off.
GC
Gain Control DAC Off.
3
GCP, GCN in High Z State.
LNAMX LNA and Mixer Off.
10
I(VDDI) = 0, CXVM,
CXVL, CXIF in High Z.
VGA
VGA/AAF Off.
6
IF2P, IF2N in High Z State.
ADC
ADC Off; Clock Buffer
13.8
Off if CK Synth. Off;
VCM in High Z State;
Clock-to-Digital Filter
Suspended; Digital
Outputs Static.
1.0
(C_REF =
4.7 µF)
Note 2
Note 2
Note 2
Depends
on C_GC
0.1
0.1
NOTES
1_{When all blocks are in standby, the master reference circuit is also put into}
standby and thus the current is reduced by a further 0.4 mA.
2_{Wake-up time is application-dependent.}
LO SYNTHESIZER
The LO synthesizer shown in Figure 4 is a fully programmable
PLL capable of 6.25 kHz resolution at input frequencies up to
300 MHz and reference clocks of up to 25 MHz. It consists of a
low-noise digital Phase-Frequency Detector (PFD), a variable
output current charge pump (CP), a 14-bit reference divider,
programmable A and B counters and a dual-modulus 8/9 pres-
caler. The A (3-bit) and B (13-bit) counters, in conjunction
with the dual 8/9 modulus prescaler, implement an N divider
with N = 8 × B + A. In addition, the 14-bit reference counter
(R Counter) allows selectable input reference frequencies, f_REF,
at the PFD input. A complete PLL (Phase-Locked Loop) can
be implemented if the synthesizer is used with an external loop
filter and VCO (Voltage Controlled Oscillator).
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