AD9742 Datasheet, PDF (9/20 Pages) Analog Devices – 12-Bit, 165 MSPS TxDAC D/A Converter

AD9742
3.3V
0.1␮F
V_REFIO
R_SET
2k⍀
CLOCK
I_REF
3.3V
REFLO
+1.20V REF
REFIO
FS ADJ
150pF
AVDD
ACOM
AD9742
PMOS
CURRENT SOURCE
ARRAY
DVDD
DCOM
CLOCK
SLEEP
SEGMENTED SWITCHES
FOR DB11–DB3
LATCHES
LSB
SWITCHES
IOUTA
IOUTB
V_DIFF = V_OUTA – V_OUTB
IOUTA
IOUTB
V_OUTB
MODE
R_LOAD
50⍀
V_OUTA
R_LOAD
50⍀
DIGITAL DATA INPUTS (DB11–DB0)
Figure 3. Simplified Block Diagram
FUNCTIONAL DESCRIPTION
Figure 3 shows a simplified block diagram of the AD9742. The
AD9742 consists of a DAC, digital control logic, and full-scale
output current control. The DAC contains a PMOS current
source array capable of providing up to 20 mA of full-scale
current (I_OUTFS). The array is divided into 31 equal currents
that make up the five most significant bits (MSBs). The next
four bits, or middle bits, consist of 15 equal current sources
whose value is 1/16th of an MSB current source. The remaining
LSBs are binary weighted fractions of the middle bits current
sources. Implementing the middle and lower bits with current
sources, instead of an R-2R ladder, enhances its dynamic perfor-
mance for multitone or low amplitude signals and helps maintain
the DAC’s high output impedance (i.e., >100 kW).
All of these current sources are switched to one or the other of
the two output nodes (i.e., IOUTA or IOUTB) via PMOS
differential current switches. The switches are based on the
architecture that was pioneered in the AD9764 family, with
further refinements to reduce distortion contributed by the
switching transient. This switch architecture also reduces
various timing errors and provides matching complementary
drive signals to the inputs of the differential current switches.
The analog and digital sections of the AD9742 have separate
power supply inputs (i.e., AVDD and DVDD) that can operate
independently over a 3.0 V to 3.6 V range. The digital section,
which is capable of operating up to a 165 MSPS clock rate,
consists of edge-triggered latches and segment decoding logic
circuitry. The analog section includes the PMOS current
sources, the associated differential switches, a 1.2 V band gap
voltage reference, and a reference control amplifier.
The DAC full-scale output current is regulated by the refer-
ence control amplifier and can be set from 2 mA to 20 mA via
an external resistor, R_SET, connected to the full-scale adjust
(FSADJ) pin. The external resistor, in combination with both
the reference control amplifier and voltage reference, V_REFIO,
sets the reference current I_REF, which is replicated to the
segmented current sources with the proper scaling factor. The
full-scale current, I_OUTFS, is 32 times I_REF.
REFERENCE OPERATION
The AD9742 contains an internal 1.2 V band gap reference.
The internal reference can be disabled by raising REFLO to
AVDD. It can also be easily overridden by an external reference
with no effect on performance. REFIO serves as either an input
or output depending on whether the internal or an external
reference is used. To use the internal reference, simply decouple
the REFIO pin to ACOM with a 0.1 mF capacitor and connect
REFLO to ACOM via a resistance less than 5 W. The internal
reference voltage will be present at REFIO. If the voltage at
REFIO is to be used anywhere else in the circuit, an external
buffer amplifier with an input bias current of less than 100 nA
should be used. An example of the use of the internal reference
is given in Figure 4.
OPTIONAL
EXTERNAL
REF BUFFER
REFLO
+1.2V REF
150pF
3.3V
AVDD
ADDITIONAL
LOAD
0.1␮F
2k⍀
REFIO
FS ADJ
AD9742
CURRENT
SOURCE
ARRAY
Figure 4. Internal Reference Configuration
An external reference can be applied to REFIO as shown in
Figure 5. The external reference may provide either a fixed refer-
ence voltage to enhance accuracy and drift performance or a
varying reference voltage for gain control. Note that the 0.1 mF
compensation capacitor is not required since the internal refer-
ence is overridden, and the relatively high input impedance of
REFIO minimizes any loading of the external reference.
3.3V
AVDD
EXTERNAL
REF
V_REFIO
REFLO
+1.2V REF
REFIO
FS ADJ
R_SET I_REF =
V_REFIO/R_SET
AD9742
150pF
AVDD
CURRENT
SOURCE
ARRAY
REFERENCE
CONTROL
AMPLIFIER
REV. 0
Figure 5. External Reference Configuration
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