AD9518-0_15 Datasheet, PDF (9/64 Pages) Analog Devices – 6-Output Clock Generator with Integrated 2.8 GHz VCO

Data Sheet
AD9518-0
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)
Table 11.
Parameter
LVPECL OUTPUT ADDITIVE TIME JITTER
CLK = 622.08 MHz; LVPECL = 622.08 MHz;
Divider = 1
CLK = 622.08 MHz; LVPECL = 155.52 MHz;
Divider = 4
CLK = 1.6 GHz; LVPECL = 100 MHz; Divider = 16
CLK = 500 MHz; LVPECL = 100 MHz; Divider = 5
Min Typ
40
80
215
245
Max Unit
fs rms
fs rms
fs rms
fs rms
Test Conditions/Comments
Distribution section only; does not include PLL and
VCO; uses rising edge of clock signal
BW = 12 kHz to 20 MHz
BW = 12 kHz to 20 MHz
Calculated from SNR of ADC method; DCC not used
for even divides
Calculated from SNR of ADC method; DCC on
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)
Table 12.
Parameter
LVPECL OUTPUT ADDITIVE TIME JITTER
Min Typ Max Unit
CLK = 2.4 GHz; VCO DIV = 2; LVPECL = 100 MHz;
210
Divider = 12; Duty-Cycle Correction = Off
fs rms
Test Conditions/Comments
Distribution section only; does not include PLL and VCO;
uses rising edge of clock signal
Calculated from SNR of ADC method
Rev. C | Page 9 of 64