AD9517-3ABCPZ Datasheet, PDF (9/80 Pages) Analog Devices – 12-Output Clock Generator with Integrated 2.0 GHz VCO

Data Sheet
AD9517-3
CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED)
Table 6.
Parameter
Min Typ
Max Unit
Test Conditions/Comments
CLK-TO-LVPECL ADDITIVE PHASE NOISE
Distribution section only; does not include PLL and VCO
CLK = 1 GHz, Output = 1 GHz
Input slew rate > 1 V/ns
Divider = 1
At 10 Hz Offset
−109
dBc/Hz
At 100 Hz Offset
−118
dBc/Hz
At 1 kHz Offset
−130
dBc/Hz
At 10 kHz Offset
−139
dBc/Hz
At 100 kHz Offset
−144
dBc/Hz
At 1 MHz Offset
−146
dBc/Hz
At 10 MHz Offset
−147
dBc/Hz
At 100 MHz Offset
−149
dBc/Hz
CLK = 1 GHz, Output = 200 MHz
Input slew rate > 1 V/ns
Divider = 5
At 10 Hz Offset
−120
dBc/Hz
At 100 Hz Offset
−126
dBc/Hz
At 1 kHz Offset
−139
dBc/Hz
At 10 kHz Offset
−150
dBc/Hz
At 100 kHz Offset
−155
dBc/Hz
At 1 MHz Offset
−157
dBc/Hz
>10 MHz Offset
−157
dBc/Hz
CLK-TO-LVDS ADDITIVE PHASE NOISE
Distribution section only; does not include PLL and VCO
CLK = 1.6 GHz, Output = 800 MHz
Input slew rate > 1 V/ns
Divider = 2
At 10 Hz Offset
−103
dBc/Hz
At 100 Hz Offset
−110
dBc/Hz
At 1 kHz Offset
−120
dBc/Hz
At 10 kHz Offset
−127
dBc/Hz
At 100 kHz Offset
−133
dBc/Hz
At 1 MHz Offset
−138
dBc/Hz
At 10 MHz Offset
−147
dBc/Hz
At 100 MHz Offset
−149
dBc/Hz
CLK = 1.6 GHz, Output = 400 MHz
Input slew rate > 1 V/ns
Divider = 4
At 10 Hz Offset
−114
dBc/Hz
At 100 Hz Offset
−122
dBc/Hz
At 1 kHz Offset
−132
dBc/Hz
At 10 kHz Offset
−140
dBc/Hz
At 100 kHz Offset
−146
dBc/Hz
At 1 MHz Offset
−150
dBc/Hz
>10 MHz Offset
−155
dBc/Hz
CLK-TO-CMOS ADDITIVE PHASE NOISE
Distribution section only; does not include PLL and VCO
CLK = 1 GHz, Output = 250 MHz
Input slew rate > 1 V/ns
Divider = 4
At 10 Hz Offset
−110
dBc/Hz
At 100 Hz Offset
−120
dBc/Hz
At 1 kHz Offset
−127
dBc/Hz
At 10 kHz Offset
−136
dBc/Hz
At 100 kHz Offset
−144
dBc/Hz
At 1 MHz Offset
−147
dBc/Hz
>10 MHz Offset
−154
dBc/Hz
Rev. E | Page 9 of 80