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AD9517-3 Datasheet, PDF (9/80 Pages) Analog Devices – 12-Output Clock Generator with Integrated 2.0 GHz VCO | |||
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Data Sheet
AD9517-3
CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED)
Table 6.
Parameter
Min Typ
Max Unit
Test Conditions/Comments
CLK-TO-LVPECL ADDITIVE PHASE NOISE
Distribution section only; does not include PLL and VCO
CLK = 1 GHz, Output = 1 GHz
Input slew rate > 1 V/ns
Divider = 1
At 10 Hz Offset
â109
dBc/Hz
At 100 Hz Offset
â118
dBc/Hz
At 1 kHz Offset
â130
dBc/Hz
At 10 kHz Offset
â139
dBc/Hz
At 100 kHz Offset
â144
dBc/Hz
At 1 MHz Offset
â146
dBc/Hz
At 10 MHz Offset
â147
dBc/Hz
At 100 MHz Offset
â149
dBc/Hz
CLK = 1 GHz, Output = 200 MHz
Input slew rate > 1 V/ns
Divider = 5
At 10 Hz Offset
â120
dBc/Hz
At 100 Hz Offset
â126
dBc/Hz
At 1 kHz Offset
â139
dBc/Hz
At 10 kHz Offset
â150
dBc/Hz
At 100 kHz Offset
â155
dBc/Hz
At 1 MHz Offset
â157
dBc/Hz
>10 MHz Offset
â157
dBc/Hz
CLK-TO-LVDS ADDITIVE PHASE NOISE
Distribution section only; does not include PLL and VCO
CLK = 1.6 GHz, Output = 800 MHz
Input slew rate > 1 V/ns
Divider = 2
At 10 Hz Offset
â103
dBc/Hz
At 100 Hz Offset
â110
dBc/Hz
At 1 kHz Offset
â120
dBc/Hz
At 10 kHz Offset
â127
dBc/Hz
At 100 kHz Offset
â133
dBc/Hz
At 1 MHz Offset
â138
dBc/Hz
At 10 MHz Offset
â147
dBc/Hz
At 100 MHz Offset
â149
dBc/Hz
CLK = 1.6 GHz, Output = 400 MHz
Input slew rate > 1 V/ns
Divider = 4
At 10 Hz Offset
â114
dBc/Hz
At 100 Hz Offset
â122
dBc/Hz
At 1 kHz Offset
â132
dBc/Hz
At 10 kHz Offset
â140
dBc/Hz
At 100 kHz Offset
â146
dBc/Hz
At 1 MHz Offset
â150
dBc/Hz
>10 MHz Offset
â155
dBc/Hz
CLK-TO-CMOS ADDITIVE PHASE NOISE
Distribution section only; does not include PLL and VCO
CLK = 1 GHz, Output = 250 MHz
Input slew rate > 1 V/ns
Divider = 4
At 10 Hz Offset
â110
dBc/Hz
At 100 Hz Offset
â120
dBc/Hz
At 1 kHz Offset
â127
dBc/Hz
At 10 kHz Offset
â136
dBc/Hz
At 100 kHz Offset
â144
dBc/Hz
At 1 MHz Offset
â147
dBc/Hz
>10 MHz Offset
â154
dBc/Hz
Rev. E | Page 9 of 80
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