AD9460_15 Datasheet, PDF (9/32 Pages) Analog Devices – 16-Bit, 80 MSPS/105 MSPS ADC

Pin No.
10
11
12 to 17, 25 to 31, 35, 37
22
23
40
41
47, 63, 75, 87
48, 64, 76, 88
49
50
51
52
53
54
55
56
57
58
59
60
61
62
65
66
67
68
69
70
71
72
73
74
77
78
79
80
81
82
83
84
85
86
89
90
100
Mnemonic
REFT
REFB
AVDD2
VIN+
VIN−
CLK+
CLK−
DRGND
DRVDD
D0− (LSB)
D0+
D1−
D1+
D2−
D2+
D3−
D3+
D4−
D4+
D5−
D5+
D6−
D6+
D7−
D7+
DCO−
DCO+
D8−
D8+
D9−
D9+
D10−
D10+
D11−
D11+
D12−
D12+
D13−
D13+
D14−
D14+
D15−
D15+ (MSB)
OR−
OR+
SFDR
AD9460
Description
Differential Reference Output. Decoupled to ground with 0.1 μF capacitor and to REFB
(Pin 11) with 0.1 μF and 10 μF capacitors.
Differential Reference Output. Decoupled to ground with a 0.1 μF capacitor and to REFT
(Pin 10) with 0.1 μF and 10 μF capacitors.
5.0 V Analog Supply (±5%).
Analog Input—True.
Analog Input—Complement.
Clock Input—True.
Clock Input—Complement.
Digital Output Ground.
3.3 V Digital Output Supply (3.0 V to 3.6 V).
D0 Complement Output Bit (LVDS Levels).
D0 True Output Bit.
D1 Complement Output Bit.
D1 True Output Bit.
D2 Complement Output Bit.
D2 True Output Bit.
D3 Complement Output Bit.
D3 True Output Bit.
D4 Complement Output Bit.
D4 True Output Bit.
D5 Complement Output Bit.
D5 True Output Bit.
D6 Complement Output Bit.
D6 True Output Bit.
D7 Complement Output Bit.
D7 True Output Bit.
Data Clock Output—Complement.
Data Clock Output—True.
D8 Complement Output Bit.
D8 True Output Bit.
D9 Complement Output Bit.
D9 True Output Bit.
D10 Complement Output Bit.
D10 True Output Bit.
D11 Complement Output Bit.
D11 True Output Bit.
D12 Complement Output Bit.
D12 True Output Bit.
D13 Complement Output Bit.
D13 True Output Bit.
D14 Complement Output Bit.
D14 True Output Bit.
D15 Complement Output Bit.
D15 True Output Bit.
Out-of-Range Complement Output Bit.
Out-of-Range True Output Bit.
SFDR Control Pin. CMOS-compatible control pin for optimizing the configuration of the
AD9460 analog front end. Connecting SFDR to AGND optimizes SFDR performance for
applications with analog input frequencies <200 MHz for 80 MSPS and 105 MSPS speed
grades. For applications with analog inputs >200 MHz, connect this pin to AVDD1 for
optimum SFDR performance; power dissipation from AVDD2 increases by ~70 mW for the
AD9460BSVZ-80 and ~20 mW for the AD9460BSVZ-105.
Rev. 0 | Page 9 of 32