AD7823_15 Datasheet, PDF (9/11 Pages) Analog Devices – 2.7 V to 5.5 V, 5s, 8-Bit ADC in 8-Lead microSOIC/DIP

AD7823
Mode 2 Operation (Automatic Power-Down)
When used in this mode of operation, the part automatically
powers down at the end of a conversion. This is achieved by
leaving the CONVST signal low until the end of the conversion.
The timing diagram in Figure 15 shows how to operate the part
in this mode. If the AD7823 is powered down, the rising edge of
the CONVST pulse causes the part to power up. When the part
has powered up (≈ 1.5 µs after the rising edge of CONVST), the
CONVST signal is brought low, and a conversion is initiated
on this falling edge of the CONVST signal. The conversion
takes 5 µs max and after this time, the conversion result is latched
into the serial shift register and the part powers down. Therefore,
when the part is operated in Mode 2, the effective conversion
time is equal to the power-up time (1.5 µs) and the SAR conver-
sion time (5 µs), i.e., 6.5 µs.
As in the case of Mode 1 operation, the rising edge of the
CONVST pulse enables the serial port of the AD7823—see
Serial Interface section. If a serial read is initiated soon after this
rising edge (Point “A”), i.e., before the end of the conversion,
then the result of the previous conversion is shifted out on pin
D_OUT. In order to read the result of the current conversion, the
user must wait at least 5 µs max after the falling edge of CONVST
before initiating a serial read. The serial port of the AD7823 is
still functional even though the AD7823 has been powered
down. Note: A serial read should not cross the reset rising edge
of CONVST.
Because it is possible to do a serial read from the part while it is
powered down, the AD7823 is powered up only to do the conver-
sion and is immediately powered down at the end of a conversion.
This significantly improves the power consumption of the part
at slower throughput rates—see Power vs. Throughput Rate
section.
Note: Although the AD7823 takes 1.5 µs to power up after
the rising edge of CONVST, it is not necessary to leave CONVST
high for 1.5 µs after the rising edge before bringing it low to
initiate a conversion. If the CONVST signal goes low before
1.5 µs in time has elapsed, the power-up time is timed out inter-
nally and a conversion is initiated. Hence the AD7823 is guaran-
teed to have always powered up before a conversion is initiated—
even if the CONVST pulsewidth is <1.5 µs. If the CONVST
width is >1.5 µs a conversion is initiated on the falling edge.
SERIAL INTERFACE
The serial interface of the AD7823 consists of three wires, a
serial clock input SCLK, serial port enable CONVST and a
serial data output D_OUT, see Figure 16 below. The serial inter-
face is designed to allow easy interfacing to most microcontrollers,
e.g., PIC16C, PIC17C, QSPI and SPI, without the need for any
gluing logic. When interfacing to the 8051, the SCLK must be
inverted. The “Microprocessor Interface” section explains how
to interface to some popular microcontrollers.
Figure 16 shows the timing diagram for a serial read from the
AD7823. The serial interface works with both a continuous and
a noncontinuous serial clock. The rising edge of the CONVST
signal RESETS a counter, which counts the number of serial
clocks to ensure the correct number of bits are shifted out of the
serial shift registers. The SCLK is ignored once the correct
number of bits have been shifted out. In order for another serial
transfer to take place, the counter must be reset by the falling
edge of the eighth SCLK. Data is clocked out from the D_OUT
line on the first rising SCLK edge after the rising edge of the
CONVST signal and on subsequent SCLK rising edges. The
D_OUT pin goes back into a high impedance state on the falling
edge of the eighth SCLK. In multipackage applications, the
CONVST signal can be used as a chip select signal. The serial
interface will not shift data out until it receives a rising edge on
the CONVST pin.
CONVST
SCLK
D_OUT
SCLK
CONVST
D_OUT
t _POWER-UP
t₁
1.5␮s
A
B
CURRENT CONVERSION
RESULT
Figure 15. Mode 2 Operation Timing
t₃
1
2
3
4
5
6
7
8
t₅
t₄
t₇
t₆
t₈
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Figure 16. Serial Interface Timing
REV. C
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