AD7708_15 Datasheet, PDF (9/44 Pages) Analog Devices – 8-/10-Channel, Low Voltage

AD7708/AD7718
TIMING CHARACTERISTICS1, 2
(AV_DD = 2.7 V to 3.6 V or AV_DD = 5 V ؎ 5%; DV_DD = 2.7 V to 3.6 V or DV_DD = 5 V ؎ 5%; AGND =
DGND = 0 V; XTAL = 32.768 kHz; Input Logic 0 = 0 V, Logic 1 = DV_DD unless otherwise noted.
Parameter
Limit at T_MIN, T_MAX
(B Version)
Unit
Conditions/Comments
t₁
t₂
Read Operation
t₃
t₄
t₅₄
t_5A4, ⁵
t₆
t₇
t₈
t₉₆
t₁₀
Write Operation
t₁₁
t₁₂
t₁₃
t₁₄
t₁₅
t₁₆
32.768
50
0
0
0
60
80
0
60
80
100
100
0
10
80
100
0
30
25
100
100
0
kHz typ
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns min
Crystal Oscillator Frequency
RESET Pulsewidth
RDY to CS Setup Time
CS Falling Edge to SCLK Active Edge Setup Time³
SCLK Active Edge to Data Valid Delay³
DV_DD = 4.5 V to 5.5 V
DV_DD = 2.7 V to 3.6 V
CS Falling Edge to Data Valid Delay³
DV_DD = 4.5 V to 5.5 V
DV_DD = 2.7 V to 3.6 V
SCLK High Pulsewidth
SCLK Low Pulsewidth
CS Rising Edge to SCLK Inactive Edge Hold Time³
Bus Relinquish Time after SCLK Inactive Edge³
SCLK Active Edge to RDY High^{3, 7}
CS Falling Edge to SCLK Active Edge Setup Time³
Data Valid to SCLK Edge Setup Time
Data Valid to SCLK Edge Hold Time
SCLK High Pulsewidth
SCLK Low Pulsewidth
CS Rising Edge to SCLK Edge Hold Time
NOTES
1_{Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DV DD) and timed from a voltage}
level of 1.6 V.
2_{See Figures 1 and 2.}
3_{SCLK active edge is falling edge of SCLK.}
4_{These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the VOL or VOH limits.}
5_{This specification only comes into play if CS goes low while SCLK is low. It is required primarily for interfacing to DSP machines.}
6_{These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the load circuit of Figure 1. The measured number is}
then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true
bus relinquish times of the part and as such are independent of external bus loading capacitances.
7_{RDY returns high after the first read from the device after an output update. The same data can be read again, if required, while RDY is high, although care should}
be taken that subsequent reads do not occur close to the next output update.
Specifications subject to change without notice.
I_SINK ^{(1.6mA WITH DV}DD ^{= 5V}
100␮A WITH DV_DD = 3V)
TO OUTPUT
PIN
50pF
1.6V
I_SOURCE
(200␮A WITH DV_DD = 5V
100␮A WITH DV_DD = 3V)
Figure 1. Load Circuit for Timing Characterization
REV. 0
–9–