AD7658_15 Datasheet, PDF (9/32 Pages) Analog Devices – 250 kSPS, 6-Channel, Simultaneous

Data Sheet
AD7656/AD7657/AD7658
TIMING SPECIFICATIONS
AVCC/DVCC = 4.75 V to 5.25 V, VDD = 5 V to 16.5 V, VSS = −5 V to −16.5 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V internal/external,
TA = TMIN to TMAX, unless otherwise noted.¹
Table 4.
Parameter
PARALLEL MODE
tCONVERT
tQUIET
Limit at TMIN, TMAX
VDRIVE < 4.75 V
VDRIVE = 4.75 V to 5.25 V
3
3
150
150
tACQ
550
t10
25
t1
60
tWAKE-UP
2
25
PARALLEL WRITE OPERATION
t11
15
t12
0
t13
5
t14
5
t15
5
PARALLEL READ OPERATION
t2
0
t3
0
t4
0
t5
45
t6
45
t7
10
t8
12
t9
6
SERIAL INTERFACE
fSCLK
18
t16
12
t172
22
t18
0.4 tSCLK
t19
0.4 tSCLK
t20
10
t21
18
550
25
60
2
25
15
0
5
5
5
0
0
0
36
36
10
12
6
18
12
22
0.4 tSCLK
0.4 tSCLK
10
18
Unit
µs typ
ns min
ns min
ns min
ns max
ms max
µs max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
MHz max
ns max
ns max
ns min
ns min
ns min
ns max
Description
Conversion time, internal clock
Minimum quiet time required between bus relinquish
and start of next conversion
Acquisition time
Minimum CONVST low pulse
CONVST high to BUSY high
STBY rising edge to CONVST rising edge
Partial power-down mode
WR pulse width
CS to WR setup time
CS to WR hold time
Data setup time before WR rising edge
Data hold after WR rising edge
BUSY to RD delay
CS to RD setup time
CS to RD hold time
RD pulse width
Data access time after RD falling edge
Data hold time after RD rising edge
Bus relinquish time after RD rising edge
Minimum time between reads
Frequency of serial read clock
Delay from CS until SDATA three-state disabled
Data access time after SCLK rising edge/CS falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time after SCLK falling edge
CS rising edge to SDATA high impedance
1 _{Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.}
2 _{A buffer is used on the data output pins for this measurement.}
200µA
I_OL
TO OUTPUT
PIN _CL
25pF
1.6V
200µA
I_OH
Figure 2. Load Circuit for Digital Output Timing Specification
Rev. D | Page 9 of 32