AD7243ARZ Datasheet, PDF (9/12 Pages) Analog Devices – LC2MOS 12-Bit Serial DACPORT

MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD7243 is via a serial bus
which uses standard protocol compatible with DSP processors
and microcontrollers. The communications channel requires a
three-wire interface consisting of a clock signal, a data signal
and a synchronization signal. The AD7243 requires a 16-bit
data word with data valid on the falling edge of SCLK. For all
the interfaces, the DAC update may be done automatically
when all the data is clocked in or it may be done under control
of LDAC.
Figures 11 to 16 show the AD7243 configured for interfacing to
a number of popular DSP processors and microcontrollers.
AD7243–ADSP-2101/ADSP-2102 Interface
Figure 11 shows a serial interface between the AD7243 and the
ADSP-2101/ADSP-2102 DSP processor. The ADSP-2101/
ADSP-2102 contains two serial ports, and either port may be
used in the interface. The data transfer is initiated by TFS going
low. Data from the ADSP-2101/ADSP-2102 is clocked into the
AD7243 on the falling edge of SCLK. When the data transfer is
complete, TFS is taken high. In the interface shown the DAC is
updated using an external timer which generates an LDAC
pulse. This could also be done using a control or decoded ad-
dress line from the processor. Alternatively, the LDAC input
could be hard wired low and in this case the update takes place
automatically on the sixteenth falling edge of SCLK.
TIMER
ADSP - 2101/
ADSP - 2102*
TFS
SCLK
DT
LDAC
AD7243*
SYNC
SCLK
SDIN
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 11. AD7243–ADSP-2101/ADSP-2102 Interface
AD7243
AD7243–DSP56000 Interface
A serial interface between the AD7243 and the DSP56000 is
shown in Figure 12. The DSP56000 is configured for Normal
Mode Asynchronous operation with Gated Clock. It is also set
up for a 16-bit word with SCK and SC2 as outputs and the FSL
control bit set to a “0.” SCK is internally generated on the
DSP56000 and applied to the AD7243 SCLK input. Data from
the DSP56000 is valid on the falling edge of SCK. The SC2
output provides the framing pulse for valid data. This line must
be inverted before being applied to the SYNC input of the
AD7243.
The LDAC input of the AD7243 is connected to DGND so the
update of the DAC latch takes place automatically on the six-
teenth falling edge of SCLK. An external timer could also be
used as in the previous interface if an external update is
required.
DSP56000
LDAC
AD7243*
SCK
STD
SC2
SCLK
SDIN
SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 12. AD7243–DSP56000 Interface
AD7243–TMS32020 Interface
Figure 13 shows a serial interface between the AD7243 and the
TMS32020 DSP processor. In this interface, the CLKX and
FSX signals for the TMS32020 should be generated using ex-
ternal clock/timer circuitry. The FSX pin of the TMS32020
must be configured as an input. Data from the TMS32020 is
valid on the falling edge of CLKX.
The clock/timer circuitry generates the LDAC signal for the
AD7243 to synchronize the update of the output with the serial
transmission. Alternatively, the automatic update mode may be
selected by connecting LDAC to DGND.
CLOCK/
TMS32020 ^TIMER
FSX
CLKX
DX
LDAC
AD7243*
SYNC
SCLK
SDIN
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 13. AD7243–TMS32020 Interface
REV. A
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